Multiple-precision fixed-point vector multiply-accumulator using shared segmentation

Abstract

This paper presents a 64-bit fixed-point vector multiply-accumulator (MAC) architecture capable of supporting multiple precisions. The vector MAC can perform one 64x64, two 32x32, four 16x16 or eight 8x8 bit signed/unsigned multiply-accumulates using essentially the same hardware as a scalar 64-bit MAC and with only a small increase in delay. The scalar MAC architecture is "vectorized" by inserting mode-dependent multiplexing into the partial product generation and by inserting mode-dependent kills in the carry chain of the reduction tree and the final carry-propagate adder. This is an example of "shared segmentation" in which the existing scalar structure is segmented and then shared between vector modes. The vector MAC is area efficient and can be fully pipelined which makes it suitable for high-performance processors and possibly dynamically reconfigurable processors.

AIR: Iterative refinement acceleration using arbitrary dynamic precision

“…Therefore, employing the least sufficient precision that produces the prescribed solution accuracy can result in higher performance without increasing power consumption. Dynamically configured ALUs according to a level of precision arithmetic were proposed in [19,20,21,22,23,24] to exploit such lower precision arithmetic benefits. In [19], a 64bit multiply accumulator can be configured according to multiple precisions to compute one 64x64, two 32x32, four 16x16, or eight 8x8 unsigned/signed multiply-accumulations using shared segmentation.…”

A Review Paper on Arithmetic and Logical Unit for Graphics Processor

“…Thus, multi-mode ALUs become more attractive. In [13] , Tan proposed a 64-bit multiply accumulator (MAC) that can compute one 64x64, two32x32, four 16x16, or eight 8x8 unsigned/signed multiplyaccumulations using shared segmentation. On the other hands, Akkas presented architectures for dual mode adders and multipliers in floating-point [14,15] , and Is seven presented a dual-mode floating-point divider [16] that supports two parallel doubleprecision divisions or one quadruple-precision division.…”

A New Architecture For Multiple-Precision Floating-Point Multiply-Add Fused Unit Design

“…The study of SIMD arithmetic unit starts with fixed-point unit. Many fixed-point optimized subword-parallel hardware structures reducing the area and cycle delay have been developed, such as subword-parallel adders [7], multipleprecision multipliers and multiply-add (MAC) units using booth encoding [8] as well as not using booth encoding [9].…”

“…The multiplier in the proposed MAF unit is able to perform either one 53-bit or two parallel 24-bit multiplications. Two methods can be used to design the multiplier, one is booth encoding [8], and the other is array multiplier [9]. Although booth encoding can reduce the number of partial products to half and make the compression tree smaller, it adds the complexity of control logic when handling two precision multiplications, which increases the latency.…”