Multiple operating points in a CMOS log-domain filter

Fox, R.M.; Mahalingam, Nagarajan

doi:10.1109/82.769779

Cited by 35 publications

(3 citation statements)

References 19 publications

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“…Georgiou reported on a total of 126µW power consumption (including an off-chip microphone but excluding the CIS stimulation) and an input DR (at the BP pole frequencies) between 51 -58dB for a 4% THD. His filters were Class-A log-domain filters with a state-elimination circuitry (to eliminate additional existing DC operating points (Fox and Nagarajan, 1999)) and a nominal power dissipation of only 40nW. It should be noted here that Georgiou performed rectification, compression and smoothing elegantly and with minimal power requirements by using a circuit that was identical to the nonlinear LP filtering stage used by Van Schaik in his IHC circuit model.…”

Section: And 2006mentioning

confidence: 99%

Analogue CMOS Cochlea Systems: A Historic Retrospective

Katsiamis¹,

Drakakis²

2011

Biomimetic Based Applications

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Section: And 2006mentioning

confidence: 99%

Analogue CMOS Cochlea Systems: A Historic Retrospective

Katsiamis¹,

Drakakis²

2011

Biomimetic Based Applications

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“…Multiplying both sides of equation (4) From this equation, it is concluded that the bias condition V0 does not depend on the inputs, hence, it would be very sensitive to the parasitic effects [3]. To resolve the bias uncertainty, a new summing structure is proposed by introduce a current source to the capacitor node, which is shown in Fig.…”

Section: Log-domain Integrators and Summermentioning

confidence: 99%

“…Those circuits usually self-biased to an unintended operating point because of the positive feedback loops used in the log-domain circuits [3]. Unlike bipolar transistor, the CMOS transistor follows the logarithmical law only in weak-inversion region.…”

Section: Introductionmentioning

confidence: 99%

Synthesis of log-domain filter with well-defined operating point

El-Masry

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)

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A new systematic approach for the design of n-th order log-domain filters is presented. By eliminating the bias uncertainty, proper working condition is guaranteed for log-domain CMOS realization. This approach is based on the inverse-follow-the-leader-feedback (IFLF) topology and DC negative feedbacks are introduced to define the bias condition. To illustrate the proposed approach, a fourth order low-pass filer is designed and simulated in HSPICE.

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Multiple operating points in a square‐root domain first‐order filter

Blas

López-Martín

Carlosena

et al. 2006

Circuit Theory & Apps

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In this paper novel corrective circuits to avoid multiple operating points in a square-root domain first-order filter are proposed. By employing a DC test it is demonstrated that the filter possesses three operating points (two stable and one unstable) and the corrective circuits enforce the proper operating mode. The corrective circuits and filter are able to operate with very low supply voltages (as low as V GS + 2V DS sat ). Moreover, a detailed analysis concerning the impact that produces the corrective circuits on the filter performance is discussed. Both measurement and simulation results are provided to validate the circuits and analysis employed. circuit simulation packages resort to the well-known Newton-Raphson method, they are able to find only one DC operating point. Recent works are focused on finding MOP by using alternative methods [6, 7], but they are neither general nor easy to be implemented.In fact the existence of MOP is not only a problem for circuit analysis but also for circuit design. Particularly in continuous time implementations this behaviour needs to be avoided in order to enforce the correct operation mode at any time. However, very limited attention has been devoted to explore MOP [8,9] by circuit designers. To solve partially this lack of research, this paper focuses on a circuit designer-oriented treatment of the MOP problem that after achieving a detailed analysis of the circuit behaviour, it provides a solution at circuit level. This methodology is applied to a square-root domain (SRD) system that exhibits MOP, but it can be readily extended to other circuits.The SRD systems [10], a subset of the so called companding systems, are an interesting alternative to develop circuits with very low supply voltage (V DD <2V GS ) required in portable equipment and systems implemented by the most modern CMOS fabrication process [11]. The companding technique exploits the current mode and the large signal behaviour of transistors to achieve a non-linear compression of the voltage swings, allowing an extended dynamic range and less sensitive of the signal/noise ratio to the reduction of supply voltage. Although there is an internally non-linear behaviour in these systems the input-output relationships remain linear [12]. This fact is obtained implementing specific non-linear blocks in such a way that the linearization arises as a whole, i.e. the internal non-linearities cancel out conveniently leading to a linear system. Often these non-linear blocks are implemented employing translinear techniques [13,14]. The first companding systems were implemented employing BJT transistors (or MOS transistors in weak inversion) exploiting their exponential I -V characteristic leading to log-domain systems [15][16][17]. Afterward the systems were realized by the quasi-quadratic law of MOS transistors to avoid the problems of mismatches and poor bandwidth of MOS devices in weak inversion region, leading to SRD systems [18,19].In this paper a SRD first-order filter is designed based on the MOS translinear l...

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Multiple operating points in a CMOS log-domain filter

Cited by 35 publications

References 19 publications

Analogue CMOS Cochlea Systems: A Historic Retrospective

Analogue CMOS Cochlea Systems: A Historic Retrospective

Synthesis of log-domain filter with well-defined operating point

Multiple operating points in a square‐root domain first‐order filter

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