Multiple defect diagnosis using no assumptions on failing pattern characteristics

Yu, Xiaochun; Blanton, R. D.

doi:10.1145/1391469.1391567

Cited by 28 publications

(6 citation statements)

References 15 publications

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“…RADAR has the advantage that much more actionable information can be collected using product ICs. Since actual ICs are not as observable as test structures, good diagnosis is required to localize and characterize product-IC failure [34][35][36]. Figure 6 shows the flow diagram of the RADAR methodology.…”

Section: Dfm Rule Evaluationmentioning

confidence: 99%

“…The flow starts with diagnosing a large number of IC failures. Here, any diagnosis methodology can be used, although a diagnosis methodology that can pinpoint the defect location with high certainty (e.g., [35]) and can effectively deal with multiple defects [34,37] is preferred to ensure accuracy. The outcome of diagnosis is a set of suspect nets or cells where the defect is believed to reside.…”

Section: Dfm Rule Evaluationmentioning

confidence: 99%

“…For instance, when more DFM rules are suspected due to poor diagnostic resolution, it obviously is unclear which one is the source of IC failure. This issue can be mitigated by better diagnosis and defect localization [34,35,52]. However, even when the defect location is precisely known, it is still possible that multiple rules are violated at this location, resulting in degraded accuracy.…”

Section: Pros/cons Of Radarmentioning

confidence: 99%

“…This framework, which we call SLIDER (Simulation of Layout-Injected Defects for Electrical Responses), also supports multiple defect injection. This is important since defect multiplicity increases [34] with escalating process complexity.…”

Section: Our Contributionmentioning

confidence: 99%

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Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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In the integrated circuit (IC) industry, all products must go through three phases before they are available in the market, namely design, manufacturing, and testing. Design, obviously, refers to the process of converting the early concepts of the product into a precise description of its implementation. Manufacturing then uses this description to fabricate the product, where the design is physically materialized onto the silicon wafer and later packaged into the product. If design and manufacturing are perfect, then every fabricated IC is completely functional, thereby obliterating the need for testing. Unfortunately, both design and manufacturing are not ideal; therefore every manufactured IC must be subject to stringent testing procedures to ensure that most bad ICs are identified and prevented from shipping to the end-users.ICs are deemed bad when they contain certain defects that cause the ICs to fail the specifications.Defects are unintended structural and/or material changes of the IC due to design/manufacturing imperfections.These physical changes may alter the electrical characteristics of the circuit, which are sometimes severe enough to lead to a failure (i.e., violation of one or more design specifications). Common defects in IC manufacturing can be caused by contaminations in the process, variations of the process conditions, or simply the difficulty to fabricate certain features of the design. The last issue is the focus of this dissertation. Defects that arise due to certain aspects of the design being sensitive to the manufacturing process with an elevated likelihood of failure are known as systematic defects. This dissertation addresses the issues related to the prevention and identification of systematic defects by analyzing a large amount of manufactured ICs that have failed testing.For systematic-defect prevention, one common approach is to use design-for-manufacturability (DFM) rules to communicate hard-to-manufacture features to designers so that these features can be minimized in the iii design. Obviously, different rules describe different features and thus their violation/adherence will have different impact on the manufacturability of the product. It is therefore desirable to measure the relative importance of the rules and how they affect product yield. To address this issue, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of DFM rules in preventing systematic defects. RADAR analyzes a large amount of test data of failed ICs to draw statistical conclusion.Taking preventive measures, such as enforcing DFM rules, is necessary to ensure sufficient product yield. Unfortunately, the amount of resource (circuit area, designer's time, etc.) dedicated to DFM can be quite limited. It is therefore impractical to anticipate and prevent every possible hard-to-manufacture design features before the product is manufactured. Thus, systematic defects can still exist. Therefore, a mechanism is required to identify systematic ...

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Section: Dfm Rule Evaluationmentioning

confidence: 99%

Section: Dfm Rule Evaluationmentioning

confidence: 99%

Section: Pros/cons Of Radarmentioning

confidence: 99%

Section: Our Contributionmentioning

confidence: 99%

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Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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“…They are therefore hard to diagnose, and more importantly, are not directly targeted by the test metrics considered here. Emerging diagnosis approaches can effectively cope with these failures [39,40], but test approaches do not typically target defects that cause multiple, simultaneously faulty sites. These chips are therefore not considered here but are analyzed in detail in Section 4.4.…”

Section: Failing-chip Selectionmentioning

confidence: 99%

Test effectiveness evaluation through analysis of readily-available tester data

Lin

Blanton

2009

2009 International Test Conference

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Test metrics and fault models continue to evolve to keep up with defect characteristics associated with ever-changing fabrication processes. Understanding the relative effectiveness of current and proposed metrics and models is therefore important for selecting the best mix of methods for achieving a desired level of quality at reasonable cost. Test-metric and fault model evaluation traditionally relies on large, time-consuming silicon-based test experiments. Specifically, tests generated for some specific metric/model are applied to real chips, and unique chip-fail detections are used as relative measures of effectiveness. To reduce the cost of evaluating new test metrics, fault models, DFT techniques, etc., this work proposes a new approach that exploits the readily-available test-measurement data in chip-failure log files. The new approach does not require the generation and application of new patterns but uses analysis results from existing tests. We demonstrate the method by comparing several metrics and models that include: (i) stuck-at, (ii) N-detect, (iii) PAN-detect (physically-aware N-detect), (iv) bridge fault models, and (v) the input pattern fault model (also more recently referred to as the gate-exhaustive metric).

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