Multipartite table methods

Abstract

A unified view of most previous table-lookup-and-addition methods (bipartite tables, SBTM, STAM, and multipartite methods) is presented. This unified view allows a more accurate computation of the error entailed by these methods, which enables a wider design space exploration, leading to tables smaller than the best previously published ones by up to 50 percent. The synthesis of these multipartite architectures on Virtex FPGAs is also discussed. Compared to other methods involving multipliers, the multipartite approach offers the best speed/area tradeoff for precisions up to 16 bits. A reference implementation is available at www.ens-lyon.fr/ LIP/Arenaire/.

Optimized Linear, Quadratic and Cubic Interpolators for Elementary Function Hardware Implementations

“…It is important to also consider that the implementations utilized in this paper use actual extracted memory instantiations as opposed to logic produced from FPGAs. Previous research [14] has utilized specific FPGAs that have embedded memories, such as Xilinx's Block RAM (BRAM). Implementations using BRAM usually have integrated columns arranged throughout the FPGA and allocate single columns of memory at a time when needed.…”

“…First, Table 7 compares of our optimized Chebyshev quadratic and cubic interpolators with an optimized bipartite table method (SBTM) [13], an optimized symmetric table additional method (STAM) [20], a Chebyshev method without any optimization and standard multipliers [18], multipartite table methods [14], a Chebyshev method with constant-correction truncated multipliers [26], an enhanced quadratic minimax method [25] and two linear approximation algorithms (DM97 [12] and Tak98 [24]). Each of the comparisons are shown for a single operation of reciprocal (1/x) mainly because most of the papers usually only present reciprocal due to its popularity for floating-point [31].…”

A high resolution DDFS design on VHDL using bipartite table method

“…LUT based [12]- [14],iterative approaches [15] and LUT free approaches [16] are the most common ones of these ways. LUTs are the tables that store the sampled data of a signal form.…”

“…1. In DDFS designs, many improvements are revealed to achieve better spectral performance [8], lower power dissipation [9], [10], higher frequency resolution [11] and smaller required area [12]- [14]. This paper presents a high resolution, LUT based DDFS design on VHDL.…”

Hardware operators for function evaluation using sparse-coefficient polynomials

“…In hardware implementation of polynomial approximations, the size of the multipliers is a major concern. Several solutions have been investigated to limit their size: argument reduction and series expansions in [1], small table and a modified multiplication in [2], or the multipartite tables method [3,4].…”