Multilevel routing with antenna avoidance

Abstract

As technology advances into nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasmainduced gate oxide degradation caused by charge accumulation on conductors.It directly influences reliability, manufacturability and yield of VLSI circuits, especially in deep-submicron technology using high density plasma. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. In this paper, we propose a novel framework for multilevel full-chip routing with antenna avoidance using built-in jumper insertion approach. Compared with the state-of-the-art multilevel routing, the experimental results show that our approach reduced 100% antenna-violated gates and results in fewer wirelength, vias, and delay increase.

An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles

“…The recent work [9] relaxes the constraint of inserting jumpers only beside the tree nodes, for which jumpers can be inserted at an arbitrary position of a tree edge. The work achieves the same time complexity as [4] for the relaxed problem. As an example shown in Figure 3, the wire segment is of 1.3Lmax long, where Lmax denotes the upper bound for antenna (i.e., any wire longer than Lmax will violate the antenna rule).…”

“…The problem of jumper insertion on a routing tree for antenna avoidance has attracted much attention in the literature recently. Ho, Chang, and Chen in [4] propose an O(V lg V )-time bottomup approach to insert jumpers in a spanning tree of V ver- tices for antenna avoidance. The work assumes that each tree node corresponds to a gate terminal and inserts jumpers only beside the tree nodes; its optimality holds only for this special condition of inserting jumpers right beside the nodes of a spanning tree.…”

A novel framework for multilevel full-chip gridless routing

“…[3,22], [4], [8,9,10], [12,13,14] by top-down uncoarsening, VMF adopts the two-stage technique of top-down uncoarsening followed by bottom-up coarsening. See Figure 1(b) for an illustration of VMF.…”

“…• The previous works [3,12,13,14,22] are grid-based multilevel router, which cannot handle designs of variable wire/via widths and spacings. Thus, they cannot effectively handle modern routing problems with nanometer electrical effects such as OPC.…”

“…Table I compares the existing multilevel routing frameworks among [3,22], [4], [8,9,10], [12,13,14], and VMF.…”