Multilevel hierarchical matrix multiplication on clusters

Hunold, Sascha; Rauber, Thomas; Rünger, Gudula

doi:10.1145/1006209.1006230

Cited by 18 publications

(15 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…For instance, Amestoy et al studied the impact of the MPI buffering implementation on the performance of sparse matrix solvers [36]. Hunold et al proposed multilevel hierarchical matrix multiplication to improve the application performance on the PC cluster [37]. A recent work by Amestoy et al considers hybrid scheduling with mixed (memory usage and FLOPS speed) equilibration objectives [13].…”

Section: Related Workmentioning

confidence: 99%

Parallel sparse LU factorization on different message passing platforms

Shen

2006

Journal of Parallel and Distributed Computing

View full text Add to dashboard Cite

Several message passing-based parallel solvers have been developed for general (nonsymmetric) sparse LU factorization with partial pivoting. Existing solvers were mostly deployed and evaluated on parallel computing platforms with high message passing performance (e.g., 1-10 µs in message latency and 100-1000 Mbytes/sec in message throughput) while little attention has been paid on slower platforms. This paper investigates techniques that are specifically beneficial for LU factorization on platforms with slow message passing. In the context of the S + distributed memory solver, we find that significant reduction in the application message passing overhead can be attained at the cost of extra computation and slightly weakened numerical stability. In particular, we propose batch pivoting to make pivot selections in groups through speculative factorization, and thus substantially decrease the interprocessor synchronization granularity. We experimented on three different message passing platforms with different communication speeds. While the proposed techniques provide no performance benefit and even slightly weaken numerical stability on an IBM Regatta multiprocessor with fast message passing, they improve the performance of our test matrices by 15-460% on an Ethernet-connected 16-node PC cluster. Given the different tradeoffs of communication-reduction techniques on different message passing platforms, we also propose a sampling-based runtime application adaptation approach that automatically determines whether these techniques should be employed for a given platform and input matrix.

show abstract

Section: Related Workmentioning

confidence: 99%

Parallel sparse LU factorization on different message passing platforms

Shen

2006

Journal of Parallel and Distributed Computing

View full text Add to dashboard Cite

show abstract

“…There are several works optimizing MMM for many cores [53][54][55][56][57][58][59][60][61][62][63][64]. The fastest implementations are given in [23] where MMM is parallelized on Intel Xeon Phi and on IBM Blue Gene/Q; an analysis is made on which loop is going to be parallelized.…”

Section: Related Workmentioning

confidence: 99%

A high-performance matrix–matrix multiplication methodology for CPU and GPU architectures

Kelefouras¹,

Kritikakou²,

Mporas³

et al. 2016

J Supercomput

View full text Add to dashboard Cite

Current compilers cannot generate code that can compete with hand-tuned code in efficiency, even for a simple kernel like Matrix-Matrix Multiplication. A key step in program optimization is the estimation of optimal values for parameters such as tile sizes and number of levels of tiling. The scheduling parameter values selection is a very difficult and time-consuming task since parameter values depend on each other; this is why they are found by using searching methods and empirical techniques. To overcome this problem, the scheduling sub-problems must be optimized together, as one problem and not separately.In this paper a Matrix-Matrix Multiplication methodology is presented where the optimum scheduling parameters are found by decreasing the search space theoretically while the major scheduling sub-problems are addressed together as one problem and not separately according to the hardware architecture parameters and input size; for different hardware architecture parameters and/or input sizes, a different implementation is produced. This is achieved by fully exploiting the software characteristics (e.g., data reuse) and hardware architecture parameters (e.g., data caches sizes and associativities), giving high quality solutions and a smaller search space. This methodology refers to a wide range of CPU and GPU architectures.

show abstract

“…Using multi-processor tasks can improve the performance of parallel programs due to a reduced communication overhead [9,13]. In previous work we have proposed a concept how to execute M-tasks on heterogenous systems and grid environments [12] and we have presented an approach to provide efficient scheduling strategies for each M-task [14].…”

Section: The Tgrid Runtime System In Detailmentioning

confidence: 99%

TGrid - Grid runtime support for hierarchically structured task-parallel programs

Hunold

Rauber

Rünger

2006

2006 IEEE International Conference on Cluster Computing

Self Cite

View full text Add to dashboard Cite

In this article we introduce a grid runtime system called TGrid which is designed to run hierarchically structured task-parallel programs on heterogenous environments and can also be used for common component-based grid programming. TGrid is built on top of a location-aware communication layer which enables the runtime system to cluster grid nodes. As a result, the component scheduler assigns a multi-processor task to a set of processors taking into account the spatial locality within the available processors. The multi-processor task directly benefits from having less network overhead and thus, the overall runtime of a gridenabled multi-processor program is reduced.

show abstract

Multilevel hierarchical matrix multiplication on clusters

Cited by 18 publications

References 8 publications

Parallel sparse LU factorization on different message passing platforms

Parallel sparse LU factorization on different message passing platforms

A high-performance matrix–matrix multiplication methodology for CPU and GPU architectures

TGrid - Grid runtime support for hierarchically structured task-parallel programs

Contact Info

Product

Resources

About