Multilevel generalized force-directed method for circuit placement

Chan, Tony F.; Cong, Jason; Sze, Kenton

doi:10.1145/1055137.1055177

Cited by 166 publications

(146 citation statements)

References 29 publications

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“…Our present work is simpler (e.g., without an "atomistic" physical analogy), and validated through parasitic extraction and timing analysis of standard-cell designs. Force-directed schemes have been proposed for many years in the realm of VLSI standard-cell and module placement; see, e.g., [14] for an overview. In the VLSI placement context, the circuit netlist provides connectivity information: energy between cells is a function of separation in the layout, and inter-cell distances can be used in the energy minimization.…”

Section: Previous Workmentioning

confidence: 99%

Key directions and a roadmap for electrical design for manufacturability

Kahng

2007

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference

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CMP fills are inserted to make metal density uniform and hence reduce post-polish height variations. Classical methods to insert fills focus on metal density uniformity, but do not take into consideration or are unable to minimize the impact of fills on circuit performance. In this paper, we develop a fill insertion method that heuristically minimizes coupling capacitance increase due to fill. Our optimization methodology builds on fill insertion guidelines previously developed in, e.g., [12] and [1]. Experiments show that the proposed optimization methods can reduce fill impact on coupling capacitances by up to 85% for 30% pattern density and up to 65% for 60% pattern density cases.

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Section: Previous Workmentioning

confidence: 99%

Key directions and a roadmap for electrical design for manufacturability

Kahng

2007

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference

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“…a log-sum-exponential function [25], which is minimized by nonlinear optimization techniques like conjugate-gradient optimization [22]. Examples of nonlinearoptimization-based placers are APlace [18] and mPL [7].…”

Section: (3) Analytical Approachesmentioning

confidence: 99%

“…Thus all quadratic placers can now represent the HPWL, as a linear metric for netlength and an efficient estimation for routed wirelength, exactly in the quadratic objective function. An important disadvantage of quadratic placers compared to nonlinear-optimization-based placers like APlace [18] and mPL [7] has been eliminated in this way, while the CPU time advantage of quadratic placers is maintained. (18) describes that the number of connections depends quadratically on the number of pins in the clique model.…”

Section: Advantages Of the Boundingbox Net Modelmentioning

confidence: 99%

Fast and Robust Quadratic Placement Combined with an Exact Linear Net Model

Spindler¹,

Johannes²

2006

2006 IEEE/ACM International Conference on Computer Aided Design

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Abstract-This paper presents a robust quadratic placement approach, which offers both high-quality placements and excellent computational efficiency. The additional force which distributes the modules on the chip in force-directed quadratic placement is separated into two forces: hold force and move force. Both of these forces are determined without any heuristics. Based on this novel systematic force implementation, we show that our iterative placement algorithm converges to an overlapfree placement. In addition, engineering change order (ECO) is efficiently supported by our placer. To handle the important trade-off between CPU time and placement quality, a deterministic quality control is presented.In addition, a new linear net model is proposed, which accurately models the half-perimeter wirelength (HPWL) in the quadratic cost function of quadratic placement. HPWL in general is a linear metric for netlength and represents an efficient and common estimation for routed wirelength. Compared with the classical clique net model, our linear net model reduces memory usage by 75%, CPU time by 23% and netlength by 8%, which is measured by the HPWL of all nets.Using the ISPD-2005 benchmark suite for comparison, our placer combined with the new linear net model has just 5.9% higher netlength but is 16× faster than APlace, which offers the best netlength in this benchmark. Compared to Capo, our placer has 9.2% lower netlength and is 5.4× faster.In the recent ISPD-2006 placement contest, in which quality is mainly determined by netlength and CPU time, our placer together with the new net model produced excellent results.

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“…simulated annealing [3], iterative partitioning based approach [4,5,6], and analytical placement approach [7,8,9,10,11,12,13,14].…”

Section: Introductionmentioning

confidence: 99%

“…Since HPWL model is not smooth and derivable, quadratic placement optimizes the quadratic form of HPWL [7,8,9,10,11,12,14], and nonlinear model placement [16] [13] [17] adopts a nonlinear estimation of HPWL model, such as the log-sum-exponential wire length approximation patented by Naylor et al [18].…”

Section: Introductionmentioning

confidence: 99%