Multilevel-Cell Phase-Change Memory: A Viable Technology

Architectural support for designing dependable non-volatile main memories

“…PCM has a number of desirable characteristics, including zero leakage power and the ability to retain cell state for more than ten years [36]. These features pave the way for PCM to be mass produced and commercialized [6,21]. Compared to DRAM, PCM has better scalability, comparable read latency, but lower per-cell endurance.…”

“…Each PCM cell can endure only a limited number of writes [6,47,50,53,65]. The exact cell endurance depends on the PCM type (i.e., Single-Level Cell (SLC), Multi-Level Cell (MLC), and Triple-Level Cell (TLC)), the fabrication technology, and the operating temperature.…”

“…Multiple resistance ranges in MLC PCMs are used to realize multiple states. Write operations in MLCs are performed using iterative programming and are verified using subsequent read verification [6,43], which ensures that the resistance of each cell is within a safe region. The verification pulses are automatically injected into a closed-loop circuit within a PCM chip, which further exacerbates the wear-out problem [6].…”

“…Write operations in MLCs are performed using iterative programming and are verified using subsequent read verification [6,43], which ensures that the resistance of each cell is within a safe region. The verification pulses are automatically injected into a closed-loop circuit within a PCM chip, which further exacerbates the wear-out problem [6]. In current prototypes, the reported cell endurance for SLC PCM is around 10 7 -10 9 writes, while it is 10 5 -10 6 in MLC PCM [6].…”

“…The verification pulses are automatically injected into a closed-loop circuit within a PCM chip, which further exacerbates the wear-out problem [6]. In current prototypes, the reported cell endurance for SLC PCM is around 10 7 -10 9 writes, while it is 10 5 -10 6 in MLC PCM [6]. Second, as memory cell sizes shrink with technology improvements, we expect lower cell endurance because the junction between the heating electrode and GST becomes weaker, and current density will increase [69].…”