Multilevel barrel shifter for CORDIC design

Yih, Shuih-Jong; Cheng, Ming-Yuan; Feng, Wu

doi:10.1049/el:19960780

Cited by 15 publications

(7 citation statements)

References 4 publications

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“…In a nutshell, our minimum delay ILP formulation comprises constraints (3), (4), (6) and objective (7). We also consider the minimum power formulation which seeks to minimize the total wire length T total subject to a given constraint on maximum delay.…”

Section: Ilp Formulationmentioning

confidence: 99%

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An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization

Zhu

Cheng

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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We propose two orthogonal approaches to logarithmic cyclic shifter design. The first method, called fanout splitting, replaces multiplexers in a conventional design with demultiplexers which have two fanouts driving the shifting and non-shifting paths separately. The use of demultiplexers has a two-fold effect; it cuts the accumulated wire load on the critical path from O(N log 2 (N )) to O(N ), and reduces the switching probabilities on the inter-stage long wires from 1/4 to 3/16. We then perform cell order optimization to further improve the delay, and formulate it as an integer linear programming problem. For the 64-bit case, the two approaches together reduce the total delay by 67.1% and dynamic power consumption by 17.6%, respectively.

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Section: Ilp Formulationmentioning

confidence: 99%

“…In essence, this method uses 3-to-1 MUXes (multiplexer) to build the shifter network. In [6] Yih et al proposed a multilevel approach to reduce the number of transmission gates in the barrel shifter.…”

Section: Introductionmentioning

confidence: 99%

An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization

Zhu

Cheng

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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“…A barrel shift register design yields minimum delay, while a logarithmic shifter design results in lower chip area [2] and reduced power consumption [3]. Several researchers have proposed efficient implementations of shifters [4,5,6] and have explored the speed and power characteristics of various shifter designs both at transistor level [3,4] and at gate level [7]. While the implementation of shifters on printed circuit boards and dedicated chips has been extensively studied, this paper addresses FPGA-based designs and performance trade-offs of large shifters.…”

Section: Introductionmentioning

confidence: 99%

Performance optimization to alleviate I/O constraints in designing large FPGA shifters

Syed

Noore

2008

IEICE Electron. Express

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This paper presents a novel design of large shift registers to overcome the problem of I/O pin bottleneck typically encountered in FPGA implementation. The proposed design uses an embedded logic recursively to decompose and synthesize the shifter operations. Compared to the conventional logic shifter, barrel shifter, and logarithmic shifter designs, the proposed approach reduces the number of I/O pins by at least 89%, and increases the available logic slices by 215%. The performance of the design is optimized by using a hybrid clocking scheme and is easily extended to multi-chip FPGA implementation.

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“…Pereira et al proposed a True Single-Phase-Clock (TSPC) high-speed barrel shifter [4], which extensively uses a pipeline structure. Yih et al discussed an area-efficient barrel shifter structure [5] in the context of the CORDIC design. Low-power barrel shifters are presented in [6] and [7].…”

Section: Introductionmentioning

confidence: 99%

Timing-driven decomposition of a fast barrel shifter

Das

Khatri

2007

2007 50th Midwest Symposium on Circuits and Systems

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In state-of-the-art Digital Signal Processing (DSP) and Graphics applications, the shifter is an important module, consuming a significant amount of delay. This paper presents a new architectural optimization approach to synthesize a faster barrel shifter block, which can be very useful to reduce the delay of the design without significantly increasing the area. We have divided the problem of generating the shifter into two steps: timing-driven selection of multiple stages for merging, and the design of the merged stage. Techniques used in these two steps help to produce a faster implementation for the overall shifter block. Our experimental data shows that the shifter block generated by our algorithm is significantly faster (11.39% on average) than the corresponding block generated by a commercially available datapath synthesis tool.

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Multilevel barrel shifter for CORDIC design

Cited by 15 publications

References 4 publications

An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization

An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization

Performance optimization to alleviate I/O constraints in designing large FPGA shifters

Timing-driven decomposition of a fast barrel shifter

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