Multilayer Graphene Nanoribbon and Carbon Nanotube Based Floating Gate Transistor for Nonvolatile Flash Memory

Abstract

Abstract-Floating gate transistor is the basic building block of nonvolatile flash memory, which is one of the most widely used memory gadgets in modern micro and nano electronic applications. Recently there has been a surge of interest to introduce a new generation of memory devices using graphene nanotechnology. In this paper we present a new floating gate transistor (FGT) design based on multilayer graphene nanoribbon (MLGNR) and carbon nanotube (CNT). In the proposed FGT a multilayer structure of graphene nanoribbon (GNR) would be used as the channel of the field effect transistor (FET) and a layer of CNTs would be used as the floating gate. We have performed an analysis of the charge accumulation mechanism in the floating gate and its dependence on the applied terminal voltages. Based on our analysis we have observed that proposed graphene based floating gate transistor could be operated at a reduced voltage compared to conventional silicon based floating gate devices. We have presented detail analysis of the operation and the programming and erasing processes of the proposed FGT, dependency of the programming and erasing current density on different parameters, impact of scaling the thicknesses of the control and tunneling oxides. These analysis are done based on the capacitance model of the device

Field emission from graphene sheets and its application in floating gate memories

“…The distribution of the value of β is shown in figure 4(B) with a median value of 2.85 and a standard deviation of 0.59. This value agrees with the operating voltage of other graphene-based devices [12,13]. We attribute the overestimation of β in the other (non-device) reports to depositing graphene on a metal instead of a dielectric, which in turn shifts the Fermi energy and lowers the barrier for tunneling.…”

“…However, Hong et al reported graphenebased FG memory structure with a write voltage of only 7 V [12]. Also, Hossain et al reported a write voltage of 12 V for a FG structure using CNTs as the FG and multilayer graphene as the channel [13]. Although the reported write voltage is lower than the current industry standard (∼20 V) [12], it is still much higher than the values predicted based on the β values previously mentioned.…”

3.3-kV 4H-SiC Split-Gate DMOSFET with Floating p+ Polysilicon for High-Frequency Applications

“…In contrast, the C GD of the FPS-DMOSFET has additional capacitance factors originating from the FPS, active gate, and n-drift, as shown in Figure 5b [20]. Therefore, the total C GD of the FPS-DMOSFET can be expressed as follows:…”

Light-Assisted/Light-Driven Memory Behaviors with Small Molecule-Fluoropolymer-Small Molecule-Stacked Floating-Gate Heterostructures

“…Emerging material-based floating-gate transistors, such as organic semiconductors, 9−12 metal oxides, 13,14 carbon nanotubes, 15,16 perovskites, 17,18 and two-dimensional materials, 19−21 have been developed widely in recent years. Rather than using conventional silicon MOSFETs, the use of these materials as an active layer or a floating-gate provides new functionalities, including mechanically flexible properties, 22,23 synaptic behaviors, 24−27 and logic-in-memory operation.…”

“…Emerging material-based floating-gate transistors, such as organic semiconductors, − metal oxides, , carbon nanotubes, , perovskites, , and two-dimensional materials, − have been developed widely in recent years. Rather than using conventional silicon MOSFETs, the use of these materials as an active layer or a floating-gate provides new functionalities, including mechanically flexible properties, , synaptic behaviors, − and logic-in-memory operation. , With this viewpoint, a photo-activated floating-gate memory device was proposed. − In these devices, photodetection and memory functions are combined in a single device, where the unnecessary signal delay can be alleviated, and the function of two different elements can be performed simultaneously so that the image recognition system can be miniaturized by reducing the metal wiring between the photodetector and the memory element.…”