Multichip free-space global optical interconnection demonstration with integrated arrays of vertical-cavity surface-emitting lasers and photodetectors

Abstract

The experimental optical interconnection module of the Free-Space Accelerator for Switching Terabit Networks (FAST-Net) project is described and characterized. Four two-dimensional (2-D) arrays of monolithically integrated vertical-cavity surface-emitting lasers (VCSEL's) and photodetectors (PD's) were designed, fabricated, and incorporated into a folded optical system that links a 10 cm x 10 cm multichip smart pixel plane to itself in a global point-to-point pattern. The optical system effects a fully connected network in which each chip is connected to all others with a multichannel bidirectional data path. VCSEL's and detectors are arranged in clusters on the chips with an interelement spacing of 140 microm. Calculations based on measurements of resolution and registration tolerances showed that the square 50-microm detector in a typical interchip link captures approximately 85% of incident light from its associated VCSEL. The measured optical transmission efficiency was 38%, with the losses primarily due to reflections at the surfaces of the multielement lenses, which were not antireflection coated for the VCSEL wavelength. The overall efficiency for this demonstration is therefore 32%. With the measured optical confinement, an optical system that is optimized for transmission at the VCSEL wavelength will achieve an overall efficiency of greater than 80%. These results suggest that, as high-density VCSEL-based smart pixel technology matures, the FAST-Net optical interconnection concept will provide a low-loss, compact, global interconnection approach for high bisection-bandwidth multiprocessor applications in switching, signal processing, and image processing.

RATS: Reactive Architectures

“…Scaleable global (i.e., chips-to-chips) interconnection fabrics that achieve minimum bisection bandwidths in the multi-terabits/sec regime may be implemented using multiple optoelectronic integrated circuits linked to each other in the manner depicted in Figure 3-1 [28]. This approach is the basis for a global chips-to-chips interconnection approach termed FAST-Net (Free-space Accelerator for Switching Terabit Networks) [29,30]. In this approach the optical I/O from any single smart pixel array (SPA) chip, located at a lens' focal plane, is linked to portions of the I/O arrays of all chips in the system.…”

“…SPA chips with integrated VCSEL/detector arrays that have emitter and receiver elements sizes of 10 and 50 µm, respectively, and with element-to-element spacing as small as 125 µm, have been evaluated in a prototype interconnection fabric [29] [30]. To fully exploit the smart pixel I/O density, the global optical interconnection module must provide flat, high resolution, near distortion-free image fields, across a wide range of ray angles, with low optical loss.…”

Minimising crosstalk in microchannel free-space optical interconnects with the presence of higher order modes

“…Several OI designs based on two dimensional VCSEL arrays have been proposed [8][9][10][11][12][13]. From these studies, it is evident that one of the major factors determining the maximum channel density and bit-error ratio is the optical crosstalk noise within the system.…”

Novel array geometries for free-space optical interconnects with improved signal-to-noise ratio

“…Several OI designs based on two dimensional VCSEL arrays have been proposed [8][9][10][11][12][13]. From these studies, it is evident that one of the major factors that determine the maximum channel density and bit-error ratio is the optical crosstalk noise within the system.…”