[1991] Proceedings. Data Compression Conference
DOI: 10.1109/dcc.1991.213345
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Multibit decoding/encoding of binary codes using memory based architectures

Abstract: We present new memory based architectures for the design of special purpose hardware for real-time compression and decompression of data. The architecture is based on a novel idea of mapping the decode/encode tree of any binary code on to a memory device that corresponds to simultaneous decoding/encoding of multiple bits. The hardware is programmable, adaptable and yields a high compression rate. Using 1 pm CMOS process technology, this could easily lead to over 100 Mbits/sec compression rate for the JPEG base… Show more

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Cited by 8 publications
(3 citation statements)
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References 7 publications
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“…Up to now, several special-purpose VLSI architectures have been proposed to implement VLC decoder system. Two classes of architectures have been discussed in the literature, namely hardwired architecture [2]- [7] and memory-based architecture [8]- [12]. Although the VLC codeword length is variable, the decoding process can still be implemented with a hardwired look-up table.…”
Section: A Generalized Prediction Methods For Modifiedmentioning
confidence: 99%
See 1 more Smart Citation
“…Up to now, several special-purpose VLSI architectures have been proposed to implement VLC decoder system. Two classes of architectures have been discussed in the literature, namely hardwired architecture [2]- [7] and memory-based architecture [8]- [12]. Although the VLC codeword length is variable, the decoding process can still be implemented with a hardwired look-up table.…”
Section: A Generalized Prediction Methods For Modifiedmentioning
confidence: 99%
“…If we use high-order tree structure to speed up the decoding process, more memory locations will be wasted to store the unused node information. Hence, we choose two-bit tree structure [11], [12] to map the VLC code onto a memory in our proposed decoder system. It can reduce about 30% of tree nodes compared with binary tree structure.…”
Section: A Tree-based Code and Tree Structurementioning
confidence: 99%
“…Because their architectures are the direct mapping of coding tables, the VLSI implementations have to be redesigned when the tables are changed. Besides, the designs in [3] and [4] use the concurrent and parallel architectures to break the bottleneck of the decoding throughput. Nevertheless, they are designed for multiple independent bit streams.…”
Section: Introductionmentioning
confidence: 99%