Multi2Sim

Ubal, Rafael; Jang, Byunghyun; Mistry, Perhaad; Schaa, Dana; Kaeli, David

doi:10.1145/2370816.2370865

Cited by 359 publications

(27 citation statements)

References 7 publications

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“…We used Multi2Sim simulator [11] to model a quad-core processor with X86 ISA, non-inclusive, write-through LRU cache; parameters depicted in Table I. Cache size is small in relation to benchmark memory usage (working set) in order to force contention. Since the purpose is to prove the SVM's ability to selectively bypass the data, two-level cache is sufficient to demonstrate the feasibility, exploiting the relationship between each core's private cache and the shared LLC.…”

Section: Methodsmentioning

confidence: 99%

Applying SVM to data bypass prediction in multi core last-level caches

Sritriratanarak

Ekpanyapong

Chongstitvatana

2015

IEICE Electron. Express

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Bypassing emerged as a performance improvement method for shared Last-Level Caches (LLC) in multicore processors where large data portions are never reused, wasting system resources. This paper proposes an alternative method to predict data bypassing using Support Vector Machine (SVM). Based on access traces obtained from a simulator, SVM is trained to generate bypass models which are integrated into the simulator to quantify LLC performance improvements. Results show that SVM can classify which data to bypass, improving LLC performance, achieving an average 6.72% miss rate decrease across SPLASH2 benchmark combinations.

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Section: Methodsmentioning

confidence: 99%

Applying SVM to data bypass prediction in multi core last-level caches

Sritriratanarak

Ekpanyapong

Chongstitvatana

2015

IEICE Electron. Express

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“…This definition matches designs where mispredictions cause the fixed pipeline stall latency c 2017 Information Processing Society of Japan such as checkpointing, which is adopted in simulators such as Multi2Sim [26], Sniper [7] and ZSim [22].…”

Section: Dynamic Variation Of Branch Misprediction Penaltymentioning

confidence: 95%

Dependence Graph Model for Accurate Critical Path Analysis on Out-of-Order Processors

Tanimoto

Ono

Inoue

2017

Journal of Information Processing

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Abstract:The dependence graph model of out-of-order (OoO) instruction execution is a powerful representation used for the critical path analysis. However, most, if not all, of the previous models are out-of-date and lack enough detail to model modern OoO processors, or are too specific and complicated which limit their generality and applicability. In this paper, we propose an enhanced dependence graph model which remains simple but greatly improves the accuracy over prior models. The evaluation results using the gem5 simulator with configurations similar to Intel's Haswell and Silvermont architecture show that the proposed enhanced model achieves CPI errors of 2.1% and 4.4% which are 90.3% and 77.1% improvements from the state-of-the-art model.

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“…A G80 functional simulator called Barra by Collange et al [27] can execute NVIDIA CUBIN files while collecting statistics. Recently, a number of CPU+GPU simulators have become available: Multi2sim [90], FusionSim [104], MV5 [45], and MacSim [1]. Recently, a number of CPU+GPU simulators have become available: Multi2sim [90], FusionSim [104], MV5 [45], and MacSim [1].…”

Section: Other Gpgpu Performance Modeling Techniquesmentioning

confidence: 99%

Performance Analysis and Tuning for General Purpose Graphics Processing Units (GPGPU)

Kim¹,

Vuduc²,

Baghsorkhi³

et al. 2012

Synthesis Lectures on Computer Architecture

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General-purpose graphics processing units (GPGPU) have emerged as an important class of shared memory parallel processing architectures, with widespread deployment in every computer class from high-end supercomputers to embedded mobile platforms. Relative to more traditional multicore systems of today, GPGPUs have distinctly higher degrees of hardware multithreading (hundreds of hardware thread contexts vs. tens), a return to wide vector units (several tens vs. 1-10), memory architectures that deliver higher peak memory bandwidth (hundreds of gigabytes per second vs. tens), and smaller caches/scratchpad memories (less than 1 megabyte vs. 1-10 megabytes). In this book, we provide a high-level overview of current GPGPU architectures and program≠ming models. We review the principles that are used in previous shared memory parallel platforms, focusing on recent results in both the theory and practice of parallel algorithms, and suggest a con≠nection to GPGPU platforms. We aim to provide hints to architects about understanding algorithm aspect to GPGPU. We also provide detailed performance analysis and guide optimizations from high-level algorithms to low-level instruction level optimizations. As a case study, we use n-body particle simulations known as the fast multipole method (FMM) as an example. We also brie˚y survey the state-of-the-art in GPU performance analysis tools and techniques. General-purpose graphics processing units (GPGPU) have emerged as an important class of shared memory parallel processing architectures, with widespread deployment in every computer class from high-end supercomputers to embedded mobile platforms. Relative to more traditional multicore systems of today, GPGPUs have distinctly higher degrees of hardware multithreading (hundreds of hardware thread contexts vs. tens), a return to wide vector units (several tens vs. 1-10), memory architectures that deliver higher peak memory bandwidth (hundreds of gigabytes per second vs. tens), and smaller caches/scratchpad memories (less than 1 megabyte vs. 1-10 megabytes). In this book, we provide a high-level overview of current GPGPU architectures and program≠ming models. We review the principles that are used in previous shared memory parallel platforms, focusing on recent results in both the theory and practice of parallel algorithms, and suggest a con≠nection to GPGPU platforms. We aim to provide hints to architects about understanding algorithm aspect to GPGPU. We also provide detailed performance analysis and guide optimizations from high-level algorithms to low-level instruction level optimizations. As a case study, we use n-body particle simulations known as the fast multipole method (FMM) as an example. We also brie˚y survey the state-of-the-art in GPU performance analysis tools and techniques. General-purpose graphics processing units (GPGPU) have emerged as an important class of shared memory parallel processing architectures, with widespread deployment in every computer class from high-end supercomputers to embedded mobile platforms. Re...

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Multi2Sim

Cited by 359 publications

References 7 publications

Applying SVM to data bypass prediction in multi core last-level caches

Applying SVM to data bypass prediction in multi core last-level caches

Dependence Graph Model for Accurate Critical Path Analysis on Out-of-Order Processors

Performance Analysis and Tuning for General Purpose Graphics Processing Units (GPGPU)

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