Multi-swarm parallel PSO: Hardware implementation

Tewolde, Girma; Hanna, Darrin M.; Haskell, Richard E.

doi:10.1109/sis.2009.4937845

Cited by 28 publications

(23 citation statements)

References 18 publications

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“…To avoid data hazards, level 2 of the pipeline is used to specify the access priorities of the cache memory to exchange data, as shown in Fig.5. The conventional pipeline approaches [14]- [16], [18]- [25] and the enhanced pipeline approach [17] cannot avoid data hazards, since the multiple hardware modules need to access the cache memory, as respectively shown in Figs.5(a) and 5(b). In the above conventional pipeline approaches, the memory access and hardware calculation are controlled by the same control unit.…”

Section: Asynchronous Control Unitmentioning

confidence: 99%

“…The PFCB is classified as one of the core modules, since its calculation is more complex than that of other modules. [14]- [16], [18]- [25] (b) Enhanced pipeline approach [17] (c) Proposed two-level pipeline …”

Section: Asynchronous Control Unitmentioning

confidence: 99%

“…The development of PSO hardware architectures can be divided into five main directions, which include serial architectures [14]- [16], serial architectures with a pipeline [17], synchronous parallel architectures [18]- [20], asynchronous parallel architectures [21], [22] and software/hardware co-design [23]- [25].…”

Section: Introductionmentioning

confidence: 99%

“…Tewolde et al [18] proposed a prototype hardware architecture for MSPSO based on the research of Koh et al [22] and Venter and Sobieszczanski-Sobieski [21]. According to these studies, an asynchronous parallel architecture for the PSO algorithm outperforms the synchronous parallel architecture when calculation tasks exhibit heterogeneity.…”

Section: Introductionmentioning

confidence: 99%

“…The calculation speed and chip cost are also balanced. However, the achieved calculation speed is much slower than that of the other hardware approaches to the PSO algorithm [18]- [20], since their experimental results show that the evaluation of the sphere function requires over 1.8 million clock cycles. The achieved performance is unacceptable for real-time applications.…”

Section: Introductionmentioning

confidence: 99%

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A Fundamental Study of Ultrahigh-Speed Hardware Architecture for Particle Swarm Optimization

Baba

Chen

2018

Journal of Signal Processing

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Particle swarm optimization (PSO) is a powerful method for dealing with the optimization of nonlinear applications such as network optimization, power system optimization and so on. The PSO algorithms enable a higher signal processing speed than conventional approaches and dedicated digital signal processor (DSP) in various application fields. However, the software implementation of PSO is extremely time-consuming when the numbers of iterations and particles become large. In some applications such as smart engine control, nuclear reactor control and so on, real-time control on the order of μm-ms is required, which is extremely difficult to achieve in an embedded system. To realize ultrahigh-speed signal processing of the aforementioned applications, several possible approaches of PSO hardware implementation are discussed and investigated in this paper. A novel hardware architecture for the PSO algorithm is employed to overcome the above difficulties. In this research, the proposed hardware architecture is implemented into a field-programmable gate array (FPGA) to evaluate its performance. The proposed hardware architecture employs two features, which are a serial architecture with two-level pipelines and an adaptive generic particle calculation block (AGPCB). It can not only achieve much faster performance than the conventional approaches but also minimize the chip cost simultaneously. The related research achievements prove that the proposed hardware architecture can greatly reduce the calculation time while achieving high efficiency. In addition, the proposed approach has compatibility with various PSO algorithms to meet the requirements of different nonlinear applications.

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