Multi-Objective Power Management for CMPs in the Dark Silicon Age

Abstract

New power management challenges in networked many-core systems arise when limitations of the dark silicon era come into reality. The main goal in the power management process is to achieve optimal power-performance efficiency considering thermal design power budget. This necessitates i) monitoring several system characteristics including both communication and computation aspects, ii) categorizing, prioritizing, and processing the information in an intelligent way, iii) and controlling a rich set of actuators. More precisely, a comprehensive Observe-Decide-Act (ODA) loop based multi-objective control approach is needed, which has access to a rich set of sensors and actuators. In this chapter, we first identify a necessary set of system parameters for monitoring such as an upper limit on total power consumption, dynamic behaviour of workloads, utilization of processing elements, per-core power consumption, load on network-on-chip, etc. We also discuss essential actuators needed for the power management process together with a multi-objective and dark silicon aware power management policy that is able to simultaneously consider all the mentioned parameters. As actuator, fine-grained voltage and frequency scaling is utilized, including near-threshold operation, per-core power gating, as well as scheduler-level actuation to maximize the system throughput while honoring the power budget.

Can Dark Silicon Be Exploited to Prolong System Lifetime?

“…In the analysis, we have considered state-of-the-art strategies for the various phases; in particular, in the two-step runtime mapping we considered MapPro and CoNA [2], and for the dynamic power management both PAM [12], which only uses PCPG, and MOC [12] using also DVFS.…”

“…To evaluate this opportunity, we defined a naive reliabilityaware approach as an extension of MapPro [2], one of the most recent region selection strategies. The strategy searches the most suitable vacant region that is close-by to the other mapped applications.…”

“…Therefore, we extended a task mapping strategy called CoNA [2], to introduce reliability awareness. The main idea for this naive reliability-aware strategy is to prevent the usage of the most aged cores by tagging as critical all the cores violating the following condition:…”

“…As a consequence, physical limits imposed by device packaging and cooling technology on peak power consumption and peak power density have made it impossible to power-on the entire chip at the same time, leading to the dark silicon problem [1]. In practice, to avoid high temperatures that would damage transistor junctures, a chip is generally constrained by a given Thermal Design Power (TDP), or recently by the more advanced Thermal Safe Power (TSP, [2]). In particular, they allow to activate only a subset of the processing cores at the nominal voltage/frequency level, i.e.…”

“…at maximum performance level, while the rest of the resources must remain power-gated idle mode. According to projections of the International Technology Roadmap for Semiconductors (ITRS) in 2013 [2], for CPU design at 22nm the percentage of dark silicon is around 50% while for 8nm it will increase to 70%; this represents a critical issue for near future many-core systems.…”