Multi-Objective Digital Design Optimization via Improved Drive Granularity Standard Cells

Cao, Linan; Bale, Simon J.; Trefzer, Martin A.

doi:10.1109/tcsi.2021.3109239

Cited by 5 publications

(3 citation statements)

References 29 publications

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“…NSGA-II [36], one of the most popular MOEAs, has been adapted as the search tool in this and our related work [37]. The fast non-dominated sorting approach and diversity preservation strategies used ensure convergence while achieving a uniform spread of Pareto-optimal solutions [38].…”

Section: Preliminaries: Evolutionary Algorithmsmentioning

confidence: 99%

Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Cao

Bale

Trefzer

2023

IET Computers & Digital Tech

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Modern electronic design automation (EDA) tools can handle the complexity of state-ofthe-art electronic systems by decomposing them into smaller blocks or cells, introducing different levels of abstraction and staged design flows. However, throughout each independently optimised design step, overheads and inefficiencies can accumulate in the resulting overall design. Performing design-specific optimisation from a more global viewpoint requires more time due to the larger search space but has the potential to provide solutions with improved performanc. In this work, a fully-automated, multi-objective (MO) EDA flow is introduced to address this issue. It specifically tunes drive strength mapping, prior to physical implementation, through MO population-based search algorithms. Designs are evaluated with respect to their power, performance and area (PPA). The proposed approach is aimed at digital circuit optimisation at the block level, where it is capable of expanding the design space and offers a set of trade-off solutions for different case-specific utilisation. We have applied the proposed multi-objective electronic design automation flow (MOEDA) framework to ISCAS-85 and EPFL benchmark circuits by using a commercial 65 nm standard cell library. The experimental results demonstrate how the MOEDA flow enhances the solutions initially generated by the standard digital flow and how simultaneously a significant improvement in PPA metrics is achieved.

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Section: Preliminaries: Evolutionary Algorithmsmentioning

confidence: 99%

Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Cao

Bale

Trefzer

2023

IET Computers & Digital Tech

Self Cite

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“…From all studies development since them, optimal digital synthesis is still a hot research topic even after more than two decades. Cao, Bale, and Trefzer have proposed multiobjective evolutionary optimization flow in [9]. Their work has shown that EDA solutions can be improved when provided a lager panel of cell libraries in a blend of multiple gate fanouts.…”

Section: A Digital Synthesis Literaturementioning

confidence: 99%

Surface versus Performance Trade-offs: A Review of Layout Techniques

Ferreira

Avignon-Meseldzija

Bénabès

et al. 2022

JICS

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Selecting the relevant layout techniques is a key point to obtain a high-performance integrated circuit. Most of the common layout techniques, beside allowing the improvement of performance, also leads to an area overhead. Moreover, this area overhead is generally not accurately evaluated. It is proposed in this review to analyze and to evaluate the surface versus performance trade-off in three types of circuits : digital, low-frequency and radiofrequency analog circuits. Each circuit is post-layout simulated using BiCMOS SiGe 55 nm technology from STMicroelectronics. The first analysis evaluates the surface, power consumption and speed trade-off in a digital circuit implementing a 16-bit gray counter, when selecting different combinations of gates from the B55 digital library. The second analysis focuses on the implementation of an accurate capacitor ratio for switched capacitor circuits and quantifies the surface versus accuracy performance. The third analysis evaluate the performance trade-off for six different layout techniques applied on a negative resistor required for a VCO.

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“…Integrated System-on-Chip (SoC) architectures are a composition of dissimilar blocks of intellectual property (IP) cores that operate at different levels of input voltage to meet the required time-related criteria [4][5][6]. Non-critical blocks consume less energy by operating at lower supply voltages (VDDL), sometimes in the sub-threshold region, while time-critical blocks require higher supply voltages (VDDH) to achieve the desired performance [7][8][9]. To ensure proper interaction between different voltage domains/cores, reliable LS circuits are necessary to maintain the signal integrity of the design, as depicted in Figure 1.…”

Section: Introductionmentioning

confidence: 99%

Input Voltage-Level Driven Split-Input Inverter Level Shifter for Nanoscale Applications

Gundala,

Basha,

Madhurima

et al. 2024

Electronics

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A level shifter (LS) appears to be highly efficient and effective in solving voltage contentions between deep sub-threshold and core voltage levels. An input voltage-level driven split-input inverter that can create common unconnected PMOS and NMOS transistors for the input inverter is proposed, which is powered and used at the input stage to achieve maximum conversion efficiency. Layout and simulation results across different corners have demonstrated that the proposed LS is highly useful for cutting-edge nanoscale applications. It can up-convert voltage from 0.2 V to 1.2 V and down-convert from 1.2 V to 0.2 V @ 1 MHz input pulse, with a level-up or level-down mean switching delay of 1.3 ns, and a power of 9.5 nW. Moreover, the LS occupies an area of 8 μm2, which is a reasonably compact size compared to the typical LS designs. Overall, the proposed voltage LS design is an efficient and effective solution that could have an ample range of applications in IoT and biomedical, wireless sensor networks.

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Multi-Objective Digital Design Optimization via Improved Drive Granularity Standard Cells

Cited by 5 publications

References 29 publications

Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Multi‐objective digital circuit block optimisation based on cell mapping in an industrial electronic design automation flow

Surface versus Performance Trade-offs: A Review of Layout Techniques

Input Voltage-Level Driven Split-Input Inverter Level Shifter for Nanoscale Applications

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