Multi-level Operation of FeFETs Memristors: the Crucial Role of Three Dimensional Effects

Lizzit, Daniel; Bernardi, Thomas; Esseni, D.

doi:10.1109/essderc55479.2022.9947169

Cited by 4 publications

(2 citation statements)

References 20 publications

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“…In principle, intermediate polarization states can be achieved by adjusting the ratio of domains with upward and downward polarization states (35)(36)(37). Thus, intermediate polarization states with the desired polarization value should be achieved through precise control of the amplitude or width of voltage pulses, which is challenging in high-density memory applications (32,38,39). In the DCC method, we can limit the current flowing through the CG and IG generated by the polarization switching to control the amount of polarization change (Fig.…”

Section: Multilevel Operation Methods For Fetftsmentioning

confidence: 99%

Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors

Kim,

Lee

2024

Sci. Adv.

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Ferroelectric transistors based on hafnia-based ferroelectrics exhibit tremendous potential as next-generation memories owing to their high-speed operation and low power consumption. Nevertheless, these transistors face limitations in terms of memory window, which directly affects their ability to support multilevel characteristics in memory devices. Furthermore, the absence of an efficient operational technique capable of achieving multilevel characteristics has hindered their development. To address these challenges, we present a gate stack engineering method and an efficient operational approach for ferroelectric transistors to achieve 16-level data per cell operation. By using the suggested engineering method, we demonstrate the attainment of a substantial memory window of 10 V without increasing the device area. Additionally, we propose a displacement current control method, facilitating one-shot programming to the desired state. Remarkably, we suggest the compatibility of these proposed methods with three-dimensional (3D) structures. This study underscores the potential of ferroelectric transistors for next-generation 3D memory applications.

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Section: Multilevel Operation Methods For Fetftsmentioning

confidence: 99%

Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors

Kim,

Lee

2024

Sci. Adv.

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“…5(b) have first attracted much attention as steep-slope transistors based on the ferroelectric NC behavior [28], [35], then they have been investigated for their potentials as memory or memristive devices [36], [37]. The modelling of FeFETs calls for computationally demanding three-dimensional simulations, because a description of the percolation source-to-drain current paths is essential to study a possible multi-level device operation [45].…”

Section: Modelling Of Ferroelectric Devicesmentioning

confidence: 99%

Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies

Esseni

Fontanini

Lizzit

et al. 2021

2021 5th IEEE Electron Devices Technology &Amp; Manufacturing Conference (EDTM)

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This paper provides a brief introduction to the phenomenological aspects of the polarization in ferrroelectric materials, and then an analysis of a few selected topics related to the modelling of ferroelectrics. The description of ferroelectric-based devices is quite challenging, particularly because the ferroelectric is frequently stacked with other dielectrics or with a semiconductor, as opposed to being placed between metal electrodes. Predictive modelling of ferroelectric devices is admittedly difficult, and thus the scrutiny and calibration of the models by comparison to sound experimental data is of paramount importance.

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FeFET Reliability Modeling for In-Memory Computing: Challenges, Perspective, and Emerging Trends

Thomann,

Amrouch

2024

IEEE Trans. Electron Devices

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Multi-level Operation of FeFETs Memristors: the Crucial Role of Three Dimensional Effects

Cited by 4 publications

References 20 publications

Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors

Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors

Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies

FeFET Reliability Modeling for In-Memory Computing: Challenges, Perspective, and Emerging Trends

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