Multi-Gbps LDPC Decoder on GPU Devices

Abstract

To meet the high throughput requirement of communication systems, the design of high-throughput low-density parity-check (LDPC) decoders has attracted significant attention. This paper proposes a high-throughput GPU-based LDPC decoder, aiming at the large-scale data process scenario, which optimizes the decoder from the perspectives of the decoding parallelism and data scheduling strategy, respectively. For decoding parallelism, the intra-codeword parallelism is fully exploited by combining the characteristics of the flooding-based decoding algorithm and GPU programming model, and the inter-codeword parallelism is improved using the single-instruction multiple-data (SIMD) instructions. For the data scheduling strategy, the utilization of off-chip memory is optimized to satisfy the demands of large-scale data processing. The experimental results demonstrate that the decoder achieves 10 Gbps throughput by incorporating the early termination mechanism on general-purpose GPU (GPGPU) devices and can also achieve a high-throughput and high-power-efficiency performance on low-power embedded GPU (EGPU) devices. Compared with the state-of-the-art work, the proposed decoder had a × 1.787 normalized throughput speedup at the same error correcting performance.

Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

“…Te memory size requirement and the run time spent in the write/read memory accesses depend on the adopted data structure for both the H matrix and message storage. Te data structure used in previous works [10][11][12][13][14] is used in this run-time analysis. In this representation, the H matrix is represented as two separate two-dimensional arrays: the frst contains the column indexes of each matrix row, which is used for the horizontal processing, and the second contains the row indexes of each matrix column, which is used for the vertical processing.…”

“…end for line 7 Vertical processing (V2C computation) and LLR update: (11) for each variable node v j connected to c i (12) for every check node c a connected to v j (13) tmp � tmp + m c a ⟶ v j (14) end for line 12 (15) L(v j ) � L(0) v j + tmp (16) for every check node c a connected to v j (17) (18) end for line 16 (19) end for line 11 (20) end for line 3…”

“…Te expansion matrix H bm is expanded to the H matrix by replacing each negative shift coefcient with a Z × Z all zeros matrix, each zero shift coefcient with a Z × Z identity matrix, and each positive shift coefcient with a right circular permutation Z × Z identity matrix. Figure 2 shows an example of the H bm expansion matrix of size (24,12) and expansion factor Z � 96, expanded to the WiMAX H matrix of size (2304,1152). Each shift coefcient is replaced by the right circular permutation of 96 × 96 identity matrices; the "0" elements are replaced by a 96 × 96 identity matrix, and the "− 1" elements are replaced by 96 × 96 all-zero matrices.…”

“…Several studies have recently focused on software implementations of LDPC decoders on multicore devices, using three soft implementation strategies for parallel processing: some works manipulate GPUs or x86 multicore to parallelize processing [10,11], others use SIMD architecture [12] to accelerate computation, and the third exploits multicore system on chip (SoC) to take advantage of hard acceleration and soft fexibility [13,14].…”

“…In [12], we proposed a multi-Gbps LDPC decoder on a GPU, using single-instruction multiple data to parallelize the processing of many received packets. Tis approach helps to achieve higher throughputs on embedded mobile devices.…”