Multi-DSP implementation of a H.264/SVC decoder

Abstract

In this paper, the implementation of a Multi-DSP based video decoder compliant with the H.264/SVC standard (14496-10 Annex G) is presented. An optimized single DSP-based decoder implementation has been splitted in two processes: the frame decoding (entropy decoding and motion compensation) and the deblocking filter. A multi-DSP device has been used to parallelize the execution of the processes. The performance has been measured using H.264/SVC sequences with different configurations.

DSP TMS320C6678 Based SHVC Encoder Implementation and its Optimization

“…Previous standard implementation: Authors in [4]suggested a DSP-based video decoder implementation compliant to H.264/SVC standard, improving the initial version performance about 40% within performance optimizations and reaching real-time for CIF sequences. Moreover, in [5], a multi-DSP based video decoder was accomplished in accordance with the H.264/SVC standard. Two optimization processes were presented: the frame decoding process and the deblocking filter one.…”