Multi-dimensional accumulation gate LDMOS with ultra-low specific on-resistance

Wu, Lijuan; Ye, Gang; Liu, Mengjiao; Ji, Liang; Zhang, Mengyuan; Zhang, Tengfei

doi:10.1016/j.mejo.2023.105860

Cited by 3 publications

(1 citation statement)

References 23 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Reference [21] proposed a field plate with highly doped N-layer beneath the oxide trench, which formed two electron accumulation layers in the on-state. Also, [22] proposed a novel multi-dimensional accumulation gate to attract more electrons, which very effectively reduced R on,sp . These all prove that the electron accumulation effect can effectively reduce the on-resistance (R on ).…”

Section: Device Structure and Principlementioning

confidence: 99%

Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect

Lyu,

Dai,

Wang

et al. 2023

Eng. Res. Express

View full text Add to dashboard Cite

A novel stepped L-shaped trench gate silicon-on-insulator (SOI) lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with N-pillar (SLTGN-LDMOS) is proposed. SLTGN-LDMOS contains a highly doped N-pillar, assisting in reducing the specific on-resistance (Ron,sp). The stepped L-shaped trench gate (SLTG) attracts electrons to attach to the edge of the trench, thus directing more current to flow along the edge, which decreases Ron,sp effectively. Furthermore, new electric field peaks are generated on the surface of the drift region, thus increasing the breakdown voltage (BV). As a result, compared with the conventional structure (C-LDMOS), the BV of SLTGN-LDMOS increases from 63 V to 162.7 V, and the Ron,sp decreases from 1.85 mΩ·cm2 to 1.46 mΩ·cm2. Then, the figure of merit (FOM1, BV2 / Ron.sp) increases remarkably from 2.15 MW/cm2 to 18.13 MW/cm2. In addition, the maximum surface temperature of SLTGN-LDMOS is 395.3 K, slightly lower than the 398.7 K of C-LDMOS.

show abstract

Section: Device Structure and Principlementioning

confidence: 99%

Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect

Lyu,

Dai,

Wang

et al. 2023

Eng. Res. Express

View full text Add to dashboard Cite

show abstract

An UMOSFET integrated with graded semi-super-junction and 3C/4H–SiC hetero-crystalline freewheeling junction

Ding,

Wei

2023

Microelectronics Journal

View full text Add to dashboard Cite

Investigating the trade-off between BV stability and ESD robustness in the n-channel LDMOS devices

Liang,

Li,

Liu

et al. 2024

Semicond. Sci. Technol.

View full text Add to dashboard Cite

The trade-off between breakdown voltage (BV) stability and electrostatic discharge (ESD) robustness in n-channel laterally diffused metal-oxide-semiconductor (nLDMOS) devices was investigated, by utilizing computer-aided design (TCAD) simulations and charge-pumping (CP) measurements. The BV stability and ESD robustness were improved by enlarging the key parameter Lj of the drift region, and introducing the step-graded doping drift region, respectively. The proposed novel nLDMOS device demonstrates superior performance, exhibiting an excellent ESD robustness of 2.0 A and a minimal 2% BV degradation after 50,000 seconds of hot carrier injection (HCI) stress, representing a significant advancement in balancing ESD protection and long-term reliability.

show abstract

Multi-dimensional accumulation gate LDMOS with ultra-low specific on-resistance

Cited by 3 publications

References 23 publications

Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect

Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect

An UMOSFET integrated with graded semi-super-junction and 3C/4H–SiC hetero-crystalline freewheeling junction

Investigating the trade-off between BV stability and ESD robustness in the n-channel LDMOS devices

Contact Info

Product

Resources

About