2018 34th Thermal Measurement, Modeling &Amp; Management Symposium (SEMI-THERM) 2018
DOI: 10.1109/semi-therm.2018.8357348
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Multi-die packaging and thermal superposition modeling

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Cited by 2 publications
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“…First, high- performance chips are laterally placed close to each other while their temperature-sensitivity and mechanical-reliability metrics are different. This is a common scenario in 2.5D package platforms [28,46,79,[82][83][84][85][86][87][88][89][90][91][92][93]. Second, high-performance chips are vertically stacked, while the thermal resistance increases with the number of stacked chips.…”
Section: Thermal Management Challenges In Heterogeneousmentioning
confidence: 99%
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“…First, high- performance chips are laterally placed close to each other while their temperature-sensitivity and mechanical-reliability metrics are different. This is a common scenario in 2.5D package platforms [28,46,79,[82][83][84][85][86][87][88][89][90][91][92][93]. Second, high-performance chips are vertically stacked, while the thermal resistance increases with the number of stacked chips.…”
Section: Thermal Management Challenges In Heterogeneousmentioning
confidence: 99%
“…This requires effective cooling very close to the heat source. However, some of the 2.5D packages have various layers, such as TIM and heat slug layers, between the heat source and the heat sink for reliability concerns at the board level [83,85,89,92]. When the heat sink has a rough contact surface and the 2.5D package has a large thermally induced or assembly warpage, the possibility of the active device cracking and failure increases after the heat sink is attached.…”
Section: Thermal Management Challenges Due To Multichipmentioning
confidence: 99%
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