Multi-Chip Modules using etched gold conductors and a high performance low permittivity photosensitive dielectric

Abstract

As a response to the ever increasing demands made on advanced electronics interconnection, a new interconnection technology based on a combination of etched printed gold conductors and a new kind of inorganic dielectric has been developed. The gold conductors are patterned to provide dense interconnection networks with conductor line widths and spacings of less than 25 gm (0.001 in). The dielectric forms insulating layers between these gold conductor planes and allows them to be interconnected through tiny holes (vias) in the dielectric of less than 50 gm diameter, giving extremely high density three dimensional multi-layers. The dielectric also has a low permittivity (around 4) along with very low dielectric loss, necessary for high speed performance and reduction of cross-talk, and is hermetic. In addition, relatively low costs are maintained. Since the first introduction of this system [1, 2] continual testing and improvements have been carried out and thousands of tiny vias have now been successfully incorporated in multi-layer circuitry. This paper reviews the latest results of this work, concentrating on botte the processing and performance of the materials in high density multi-layer circuits.