Abstract:In this paper we describe the architecture of MTASC, a multithreaded associative SIMD processor, and a cycle-accurate instruction set simulator for that architecture. We show, through simulations of a set of five associative benchmarks, that this architecture is capable of significantly improving the performance of associative code over a singlethreaded architecture, especially for processors with a large number of PEs. Furthermore, we show that the amount of improvement in performance is highly dependent on t… Show more
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