mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator

Zhao, Zhongyuan; Kwon, Hyoukjun; Kuhar, Sachit; Sheng, Weiguang; Mao, Zhigang; Krishna, Tushar

doi:10.1109/ispass.2019.00040

Cited by 27 publications

(15 citation statements)

References 24 publications

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“…mRNA [146] is a mapper that performs design space exploration to find the optimal mapping targeting the re-configurable DNN accelerator MAERI [137]. Similarly to other design space exploration tools, it explores all the possible permutations of the for loops of the Conv layer 7-nested loop representation and all the possible combinations of tiling factors.…”

Section: Tools For Design Space Exploration (Dse)mentioning

confidence: 99%

Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead

et al. 2020

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Currently, Machine Learning (ML) is becoming ubiquitous in everyday life. Deep Learning (DL) is already present in many applications ranging from computer vision for medicine to autonomous driving of modern cars as well as other sectors in security, healthcare, and finance. However, to achieve impressive performance, these algorithms employ very deep networks, requiring a significant computational power, both during the training and inference time. A single inference of a DL model may require billions of multiply-and-accumulated operations, making the DL extremely compute-and energy-hungry. In a scenario where several sophisticated algorithms need to be executed with limited energy and low latency, the need for cost-effective hardware platforms capable of implementing energy-efficient DL execution arises. This paper first introduces the key properties of two brain-inspired models like Deep Neural Network (DNN), and Spiking Neural Network (SNN), and then analyzes techniques to produce efficient and high-performance designs. This work summarizes and compares the works for four leading platforms for the execution of algorithms such as CPU, GPU, FPGA and ASIC describing the main solutions of the state-of-the-art, giving much prominence to the last two solutions since they offer greater design flexibility and bear the potential of high energy-efficiency, especially for the inference process. In addition to hardware solutions, this paper discusses some of the important security issues that these DNN and SNN models may have during their execution, and offers a comprehensive section on benchmarking, explaining how to assess the quality of different networks and hardware systems designed for them.

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Section: Tools For Design Space Exploration (Dse)mentioning

confidence: 99%

Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead

et al. 2020

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“…Mappers for Spatial Accelerators: Most prior works focus on developing mappers specific to their architectures. For example, mRNA [28] for MAERI [7], Auto-TVM [29] for the GEMM core of the VTA architecture [30] limiting their applicability to generic spatial accelerators. Mapping optimizers such as Interstellar [31], dMazeRunner [32] are specific to convolutions and fix certain aspects of the dataflow (such as choice parallel loops and loop order), constraining the space.…”

Section: Related Workmentioning

confidence: 99%

Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication

Moon¹,

Kwon²,

Jeong³

et al. 2021

Preprint

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There is a growing interest in custom spatial accelerators for machine learning applications. These accelerators employ a spatial array of processing elements (PEs) interacting via custom buffer hierarchies and networks-on-chip. The efficiency of these accelerators comes from employing optimized dataflow (i.e., spatial/temporal partitioning of data across the PEs and fine-grained scheduling) strategies to optimize data reuse. The focus of this work is to evaluate these accelerator architectures using a tiled general matrix-matrix multiplication (GEMM) kernel. To do so, we develop a framework that finds optimized mappings (dataflow and tile sizes) for a tiled GEMM for a given spatial accelerator and workload combination, leveraging an analytical cost model for runtime and energy. Our evaluations over five spatial accelerators demonstrate that the tiled GEMM mappings systematically generated by our framework achieve high performance on various GEMM workloads and accelerators.

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“…[12,38] maximized the psum reuse, and [3] maximized weight reuse in RF and psum reuse in SPM and did not explore other execution methods. Likewise, [15,37,39,40] considered a batch size of N = 1 images, missing the opportunities for weight reuse. Thus, prior techniques organized the loops in certain ways and without explicit modeling of the complete spatiotemporal execution, they lacked information about different execution methods.…”

Section: Related Workmentioning

confidence: 99%

“…Pruning the search space: The space of execution methods is vast because, total options for multi-level tiling of the loop-nest range from several hundred to thousands [39] and for each tiling configuration, loops are reordered in numerous ways. For example, we can organize a 7-deep loopnest of convolution into 7!…”

Section: Related Workmentioning

confidence: 99%

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dMazeRunner

Dave

Kim

Avancha

et al. 2019

ACM Trans. Embed. Comput. Syst.

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Dataflow accelerators feature simplicity, programmability, and energy-efficiency and are visualized as a promising architecture for accelerating perfectly nested loops that dominate several important applications, including image and media processing and deep learning. Although numerous accelerator designs are being proposed, how to discover the most efficient way to execute the perfectly nested loop of an application onto computational and memory resources of a given dataflow accelerator ( execution method ) remains an essential and yet unsolved challenge. In this paper, we propose dMazeRunner -- to efficiently and accurately explore the vast space of the different ways to spatiotemporally execute a perfectly nested loop on dataflow accelerators (execution methods). The novelty of dMazeRunner framework is in: i) a holistic representation of the loop nests, that can succinctly capture the various execution methods, ii) accurate energy and performance models that explicitly capture the computation and communication patterns, data movement, and data buffering of the different execution methods, and iii) drastic pruning of the vast search space by discarding invalid solutions and the solutions that lead to the same cost. Our experiments on various convolution layers (perfectly nested loops) of popular deep learning applications demonstrate that the solutions discovered by dMazeRunner are on average 9.16× better in Energy-Delay-Product (EDP) and 5.83× better in execution time, as compared to prior approaches. With additional pruning heuristics, dMazeRunner reduces the search time from days to seconds with a mere 2.56% increase in EDP, as compared to the optimal solution.

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mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator

Cited by 27 publications

References 24 publications

Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead

Hardware and Software Optimizations for Accelerating Deep Neural Networks: Survey of Current Trends, Challenges, and the Road Ahead

Evaluating Spatial Accelerator Architectures with Tiled Matrix-Matrix Multiplication

dMazeRunner

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