MPSoC architecture for H.264/AVC intra prediction chain on SoCLiB platform and FPGA technology

Belhadj, Nidhameddine; Turki, M.; Marrakchi, Zied; Ayed, Mohamed Ali Ben; Nouri, Mohammad; Mehrez, Habib

doi:10.1109/sta.2013.6783133

Cited by 2 publications

(1 citation statement)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Other building blocks such as transform, entropy encoders or decoders and motion estimation can be found in [17,18,26,33]. In [4] a codec architecture based on processor cores implemented on an FPGA is given. It results in similar performance points as processor based software implementations.…”

Section: Hardware Architectures For Video Codingmentioning

confidence: 99%

Architecture of a Low Latency H.264/AVC Video Codec for Robust ML based Image Classification

Steinert

Stabernack

2022

J Sign Process Syst

View full text Add to dashboard Cite

The use of neural networks is considered as the state of the art in the field of image classification. A large number of different networks are available for this purpose, which, appropriately trained, permit a high level of classification accuracy. Typically, these networks are applied to uncompressed image data, since a corresponding training was also carried out using image data of similar high quality. However, if image data contains image errors, the classification accuracy deteriorates drastically. This applies in particular to coding artifacts which occur due to image and video compression. Typical application scenarios for video compression are narrowband transmission channels for which video coding is required but a subsequent classification is to be carried out on the receiver side. In this paper we present a special H.264/Advanced Video Codec (AVC) based video codec that allows certain regions of a picture to be coded with near constant picture quality in order to allow a reliable classification using neural networks, whereas the remaining image will be coded using constant bit rate. We have combined this feature with the ability to run with lowest latency properties, which is usually also required in remote control applications scenarios. The codec has been implemented as a fully hardwired High Definition video capable hardware architecture which is suitable for Field Programmable Gate Arrays.

show abstract