MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs

Chen, Tung-Chieh; Yuh, Ping-Hung; Chang, Yao-Wen; Huang, Fwu-Juh; Liu, Tien-Yueh

doi:10.1109/tcad.2008.927760

Cited by 37 publications

(30 citation statements)

References 26 publications

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“…Also, APlace3 [15] crashes on every MMS circuit as reported in [47] thus is not included in the results. MP-tree [6] and CG [4] are not available due to the industrial copyrights, while their results on MMS benchmarks are also not available. However, as both of them have been outperformed by NTUplace3-unified [13] with on average 21% and 9% shorter wirelength (reported in Table V of [13]), we do not include them in our experiments.…”

Section: Experiments and Resultsmentioning

confidence: 99%

“…(6). By differentiating it we derive the gradient vector to direct density cost reduction, where by Eq.…”

Section: E Advantage Analysismentioning

confidence: 99%

“…Unlike traditional SA based floorplanners and macro placers [4], [6], [32], [46] which perturb floorplan expression then physically realize it, mLG uses SA to directly control macro motion.…”

Section: Macro Legalization (Mlg)mentioning

confidence: 99%

“…Location and orientation of macros are determined and fixed at first, while placement follows to optimize only standard cells in the global scale. MPtree [6] packs macros along the chip boundaries. A constraintgraph (CG) algorithm [4] uses mathematical programming to optimize displacement, macro positions and orientations.…”

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confidence: 99%

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ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits

Zhuang

Chen

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We propose eP lace-M S, an electrostatics based placement algorithm for large-scale mixed-size circuits. ePlace-MS is generalized, flat, analytic and nonlinear. The density modeling method eDensity is extended to handle the mixedsize placement. We conduct detailed analysis on the correctness of the gradient formulation and the numerical solution, as well as the rationale of direct-current removal and the advantages over prior density functions. Nesterov's method is used as the nonlinear solver, which shows high yet stable performance over mixed-size circuits. The steplength as the inverse of Lipschitz constant of the gradient function, while we develop a backtracking method to prevent overestimation. An approximated nonlinear preconditioner is developed to minimize the topological and physical differences between large macros and standard cells. Besides, we devise a simulated annealer to legalize the layout of macros and use a second-phase global placement to reoptimize the standard cell layout. All the above innovations are integrated into our mixed-size placement prototype ePlace-MS, which outperforms all the related works in literature with better quality and efficiency. Compared to the leading-edge mixed-size placer NTUplace3 [13], ePlace-MS produces up to 22.98% and on average 8.22% shorter wirelength over all the sixteen modern mixed-size (MMS) benchmark circuits with the same runtime.

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Section: Experiments and Resultsmentioning

confidence: 99%

“…(6). By differentiating it we derive the gradient vector to direct density cost reduction, where by Eq.…”

Section: E Advantage Analysismentioning

confidence: 99%

Section: Macro Legalization (Mlg)mentioning

confidence: 99%

mentioning

confidence: 99%

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ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits

Zhuang

Chen

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The works [7,8,10] classify mixed-size placement algorithms into three types: (1) One-stage mixed-size placement places macros and standard cells simultaneously; SimPL [11], ComPLx [12], MAPLE [13], mPL6 [3], NTUplace3 [6], Hsu and Chang [10], and ePlace-MS [16] belong to this type. (2) Constructive mixed-size placement places macros constructively, free of overlaps; Capo [2] and FLOP [20] are two examples; (3) Three-stage mixed-size placement divides the mixed-size placement into the following three stages: placement prototyping, macro placement, and standard-cell placement; XDP [9], CG [4], MP-tree [7] and CP-tree [8] belong to this type.…”

Section: Introductionmentioning

confidence: 99%

Circular-contour-based obstacle-aware macro placement

Chiou

Chang

Chen

et al. 2016

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

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A modern system-on-a-chip (SoC) typically consists of a large number of mixed-size circuit components with big macros and standard cells. Pre-placed macros (obstacles) and big macros further complicate such mixedsize circuit placement, and thus often make existing works fail to obtain a legal mixed-size placement. In this paper, we present an obstacle-aware macro placement algorithm which locates big macros to simultaneously optimize wirelength and routability. We first propose a circular contour to characterize the region formed by all obstacles. With the circular contour, we can effectively avoid the overlap between movable macros and obstacles, and simultaneously optimize the shape and area of the region for standard-cell placement. Unlike most previous macro placers that spend much time on searching for a feasible solution, our circular packing scheme packs movable macros around the obstacle contour to generate feasible solutions efficiently, and thus assists simulated annealing to focus on solution-quality optimization. Experimental results show that our algorithm can achieve the best quality, compared to manual designs provided by industry and leading academic mixed-size placers.

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