MOVPE growth of GaN on Si substrate with 3C-SiC buffer layer

Katagiri, Masayoshi; Fang, Hao; Miyake, Hideto; Hiramatsu, Kazumasa; Oku, Hirosuke; Asamura, Hidetoshi; Kawamura, K.

doi:10.7567/jjap.53.05fl09

Cited by 23 publications

(14 citation statements)

References 17 publications

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“…Better quality was obtained for SiC grown on off-axis Si, with a FWHM of 0.43° (1548 arcsec) at a thickness of 1100 nm. Importantly, this value is comparable to the value reported for SiC grown on 4° off-axis Si at the much higher temperature of 1350 °C 11 . A suitable lower temperature process should suffer less from thermal expansion coefficient mismatch and result in films with lower residual stress and reduced wafer bow, but still deposit films with similar crystal quality.…”

Section: Resultssupporting

confidence: 84%

“…3 ) increased with thickness, indicating the lateral coalescence of domains, but 3D growth still dominated due to insufficient surface diffusion energy relative to its larger terrace width. The ~550 nm on-axis SiC (RMS roughness of ~9.60 nm) is smoother than the SiC grown at a similar temperature of 1220 °C by another group (RMS roughness of larger than 18 nm for ~500 nm 3C-SiC) 11 , but rougher than the SiC grown at a higher temperature of 1350 °C (RMS roughness of 2.9 nm for ~500 nm) 17 , indicating that the elevated temperature aids the smoothening process during the deposition of SiC.…”

Section: Resultsmentioning

confidence: 80%

“…Previous studies have shown that the strain relaxation and dislocation density reduction in the grown GaN/3C-SiC/Si layers are affected by the thickness, roughness, off-cut angle, curvature magnitude and shape of the 3C-SiC/Si template 3 9 10 11 . Both thin (50 nm) and thick (2500 nm) SiC films have been reported to lead to the generation of cracks in GaN layers 2 11 , whereas an intermediate thickness of 700 ~ 1000 nm 3C-SiC/Si acted as the best template to suppress crack generation. The roughness of SiC was found to increase with its thickness 9 11 12 , and that a reduction of surface roughness by mechanical polishing led to an improvement in GaN crystalline quality and a reduced wafer bow 9 .…”

mentioning

confidence: 99%

“…Both thin (50 nm) and thick (2500 nm) SiC films have been reported to lead to the generation of cracks in GaN layers 2 11 , whereas an intermediate thickness of 700 ~ 1000 nm 3C-SiC/Si acted as the best template to suppress crack generation. The roughness of SiC was found to increase with its thickness 9 11 12 , and that a reduction of surface roughness by mechanical polishing led to an improvement in GaN crystalline quality and a reduced wafer bow 9 . By using SiC grown on 4° off-axis Si substrate, a reduction in the threading dislocation density in GaN was observed 9 .…”

mentioning

confidence: 99%

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Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates

Wang

Walker

Chai

et al. 2015

Sci Rep

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A thin, chemically inert 3C-SiC layer between GaN and Si helps not only to avoid the “melt-back” effect, but also to inhibit the crack generation in the grown GaN layers. The quality of GaN layer is heavily dependent on the unique properties of the available 3C-SiC/Si templates. In this paper, the parameters influencing the roughness, crystalline quality, and wafer bow are investigated and engineered to obtain high quality, low roughness 3C-SiC/Si templates suitable for subsequent GaN growth and device processing. Kinetic surface roughening and SiC growth mechanisms, which depend on both deposition temperature and off-cut angle, are reported for heteroepitaxial growth of 3C-SiC on Si substrates. The narrower terrace width on 4° off-axis Si enhances the step-flow growth at 1200 °C, with the roughness of 3C-SiC remaining constant with increasing thickness, corresponding to a scaling exponent of zero. Crack-free 3C-SiC grown on 150-mm Si substrate with a wafer bow of less than 20 μm was achieved. Both concave and convex wafer bow can be obtained by in situ tuning of the deposited SiC layer thicknesses. The 3C-SiC grown on off-axis Si, compared to that grown on on-axis Si, has lower surface roughness, better crystallinity, and smaller bow magnitude.

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Section: Resultssupporting

confidence: 84%

Section: Resultsmentioning

confidence: 80%

mentioning

confidence: 99%

mentioning

confidence: 99%

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Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates

Wang

Walker

Chai

et al. 2015

Sci Rep

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“…SiC has many advantages over direct GaN growth on Si such as acting as a chemical barrier to the Si substrate, lower lattice constant and thermal expansion coefficient mismatch, higher thermal conductivity, and higher breakdown voltages . To date, there are few studies of the desirable 3C‐SiC buffer layer properties for optimal subsequent GaN deposition . An important factor in deposition of a GaN epitaxial layer is the ability to control the residual stress of the GaN layer as GaN deposition on Si introduces residual tensile stress due to the thermal expansion coefficient mismatch .…”

Section: Introductionmentioning

confidence: 99%

Effect of SiC‐on‐Si template residual stress on GaN residual stress and crystal quality

Chai

Walker

Wang

et al. 2016

Physica Status Solidi (b)

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The thermal expansion coefficient mismatch between GaN and SiC is lower than between GaN and Si. However it is usually observed that GaN on SiC/Si templates has higher tensile stress than GaN directly on Si. To provide an insight into the relationship between SiC template residual stress and GaN overlayer residual stress and crystal quality, we have analyzed the in‐plane residual stress gradient present in GaN/SiC microstructure arrays of various dimensions and shapes using micro‐Raman spectroscopy. It was found that the GaN overlayer residual stress is directly proportional to the SiC buffer layer residual stress. GaN films with lower residual stress also resulted in GaN films with improved crystal quality. Our study shows that the frequently encountered problems of high tensile stress in GaN films deposited on SiC templates is due to the high tensile residual stress in the SiC layers. The poorer GaN crystal quality deposited on SiC templates reported in literature is also likely due to the high tensile stress in the SiC templates. In order to grow GaN films with sufficient compressive stress and crystal quality for subsequent device processing, it is crucial to reduce the high tensile stress present in the SiC templates.

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High Thermal Stability and Low Thermal Resistance of Large Area GaN/3C‐SiC/Diamond Junctions for Practical Device Processes

Kagawa,

Cheng,

Kawamura

et al. 2023

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Thermal management is critical in contemporary electronic systems, and integrating diamond with semiconductors offers the most promising solution to improve heat dissipation. However, developing a technique that can fully exploit the high thermal conductivity of diamond, withstand high‐temperature annealing processes, and enable mass production is a significant challenge. In this study, the successful transfer of AlGaN/GaN/3C‐SiC layers grown on Si to a large‐size diamond substrate is demonstrated, followed by the fabrication of GaN high electron mobility transistors (HEMTs) on the diamond. Notably, no exfoliation of 3C‐SiC/diamond bonding interfaces is observed even after annealing at 1100 °C, which is essential for high‐quality GaN crystal growth on the diamond. The thermal boundary conductance of the 3C‐SiC‐diamond interface reaches ≈55 MW m−2 K−1, which is efficient for device cooling. GaN HEMTs fabricated on the diamond substrate exhibit the highest maximum drain current and the lowest surface temperature compared to those on Si and SiC substrates. Furthermore, the device thermal resistance of GaN HEMTs on the diamond substrate is significantly reduced compared to those on SiC substrates. These results indicate that the GaN/3C‐SiC on diamond technique has the potential to revolutionize the development of power and radio‐frequency electronics with improved thermal management capabilities.

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MOVPE growth of GaN on Si substrate with 3C-SiC buffer layer

Cited by 23 publications

References 17 publications

Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates

Kinetic surface roughening and wafer bow control in heteroepitaxial growth of 3C-SiC on Si(111) substrates

Effect of SiC‐on‐Si template residual stress on GaN residual stress and crystal quality

High Thermal Stability and Low Thermal Resistance of Large Area GaN/3C‐SiC/Diamond Junctions for Practical Device Processes

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