MOSFETs’ Electrical Performance in the 160-nm BCD Technology Process With the Diamond Layout Shape

Barri, D.; Vacula, Patrik; Gresl, T.; Svancara, P.; Kote, Vlastimil; Jakovenko, J.; Voves, J.

doi:10.1109/ted.2020.3000744

Cited by 2 publications

(2 citation statements)

References 26 publications

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“…; however, all of them involve high investments. Another low-cost alternative, not yet widespread in semiconductors and integrated circuits (ICs) industries, is to use nonconventional gate shapes [5] (Diamond/hexagonal [6], Octagonal [7], Ellipsoidal [8]) for MOSFETs. This layout approach is capable of boosting the analog and digital electrical performances, including ionizing radiation tolerance of MOSFETs, thanks to the: I-"Longitudinal Corner Effect" (LCE), which is responsible for boosting the resultant longitudinal electric field (RLEF) in the channel region of the MOSFET and consequently its drift velocity [𝜗 ⃗ =.𝐿𝐸𝐹 ⃗⃗⃗⃗⃗⃗⃗⃗⃗ , where  is the average value of the mobility of mobile charge carriers along the channel (Qmcc)], and subsequently the drain to electric current source (𝐼 𝐷𝑆 ⃗⃗⃗⃗⃗⃗ = 𝑄𝑚𝑐𝑐.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, the electric current between the regions of the drain and source (IDS) of the MOSFET tends to further flow by the edges of the channel (infinitesimal CMs with the smallest channel lengths); III-"Deactivation of Parasitic MOSFETs in Bird's Beaks Regions" (DEPAMBBRE), which is capable of improving the ionizing radiation tolerance of the Total Ionizing Dose (TID) of MOSFETs, as the RLEF lines are curves in the edges of the channel of the MOSFET. Consequently, they are able to deactivate the parasitic MOSFETs in the Bird's Beak region [6][7][8].…”

Section: Introductionmentioning

confidence: 99%

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Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs

DaSilva

Gimenez

2022

JICS

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Previous studies have been showing that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal) and Ellipsoidal gate shapes for implementing of the planar and three-dimensional MOSFETs are is capable of boosting their analog and digital electrical performances and also by reducing used die areas, when we replace conventional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), that present rectangular gate shape, by those implemented by these innovative layout styles. In order to further boosting these features obtained by the use of first generation of layout styles, we are introducing one of elements of the second generation of layout styles for MOSFETs, intitled Half-Diamond. This new proposal is an evolution of Diamond layout style, in which it is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivation of Parasitic MOSFETs in Bird’s Beaks Regions (DEMPAMBBRE) effects of the first generation and also of further reducing the dimensions of conventional MOSFETs (CM) in which the Diamond MOSFETs have gotten to do. Thus, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond and Conventional layout styles, regarding the analog Complementary MOS (CMOS) integrated circuits (ICs) applications, which their channel lengths are not usually designed with the minimum dimension (Lmin) allowed by the CMOS ICs manufacturing processes. The results obtained show that, for instance, the saturation drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in CM counterparts. Besides, by using Half-Diamond layout style, it is possible of further reducing the die areas of analog CM and consequently of the analog CMOS ICs applications, in comparison to those reached by the use of Diamond layout styles, regarding a 180 nm Bulk CMOS ICs technology node.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs

DaSilva

Gimenez

2022

JICS

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Comparison of Measured Data Given by Automatized Measurement Methodology with the Analytical Expression of DLS MOSFET

Barri

Jakovenko

2020

2020 International Conference on Applied Electronics (AE)

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At this moment in the field of FPGA, only RAM tests have been carried out to evaluate its performance but these works have not focused on tracking memory usage in real time, this paper proposes a design for monitoring the memory of an embedded system, in the logical part, making use of the communication between the FPGA and the HPS. In addition, the HPS has implemented a web service that allows to visualize a graph of the monitoring in real time. The proposed design can be an introduction to the development of applications that can be specifically monitored for a component of the embedded system in FPGA, because FPGA is currently being used for different purposes such as machine learning, real-time image processing, mining of Bitcoins, among others. These applications are quite robust, which implies a high demand for processing for the embedded system.

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MOSFETs’ Electrical Performance in the 160-nm BCD Technology Process With the Diamond Layout Shape

Cited by 2 publications

References 26 publications

Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs

Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs

Comparison of Measured Data Given by Automatized Measurement Methodology with the Analytical Expression of DLS MOSFET

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