MoS<inf>2</inf> FET fabrication and modeling for large-scale flexible electronics

Reproducible Performance Improvements to Monolayer MoS2 Transistors through Exposed Material Forming Gas Annealing

“…In summary, the observed performance benefits of the EM-FGA process are threefold: (i) by drastically reducing the interface contamination and trap charges, a controlled V T shift on both the back gate and top gate closer to the ideal value was achieved, which in turn improves the performance and reproducibility of FETs fabricated using this approach closer to the level needed for integration in logic circuits, , (ii) ohmic metal–MoS 2 contacts were achieved, evident by the linear I DS – V DS characteristics, with a low contact resistance, and (iii) important FET characteristics including μ FE , subthreshold swing, and I on / I off ratio were maintained at values previously reported for FETs fabricated from MoS 2 sourced from traditional mechanical exfoliation. Furthermore, the benefits of EM-FGA were achieved using only a tube furnace operating at relatively high pressures, that is, 350 Pa (2.6 Torr), which makes the technique straightforward to implement without the need for highly specialized equipment. − ,, The EM-FGA process is gentle and minimizes damage to the large monolayers obtained through metal-mediated exfoliation, unlike other commonly used cleaning techniques that utilize UV–ozone, which has been shown to create disadvantageous MoO x or even eliminate transistor behavior in FETs. ,, We expect EM-FGA to be a critical component of the streamlined processing of 2D materials obtained using increasingly widespread metal-mediated exfoliation techniques. ,, Finally, to better describe the mechanism underlying the improved FET performance in this work, we performed several complimentary measurements on the monolayers from which the FETs were fabricated, as described next.…”

“…In summary, the observed performance benefits of the EM-FGA process are threefold: (i) by drastically reducing the interface contamination and trap charges, a controlled V T shift on both the back gate and top gate closer to the ideal value was achieved, which in turn improves the performance and reproducibility of FETs fabricated using this approach closer to the level needed for integration in logic circuits, 58,63 (ii) ohmic metal−MoS 2 contacts were achieved, evident by the linear I DS −V DS characteristics, with a low contact resistance, and (iii) important FET characteristics including μ FE , subthreshold swing, and I on /I off ratio were maintained at values previously reported for FETs fabricated from MoS 2 sourced from traditional mechanical exfoliation. Furthermore, the benefits of EM-FGA were achieved using only a tube furnace operating at relatively high pressures, that is, 350 Pa (2.6 Torr), which makes the technique straightforward to implement without the need for highly specialized equipment.…”

Device modelling of bendable MOS transistors

“…Several modelling teams deal with the compact modelling of bulk MOSFET and advanced technologies such as double-gate (DG) MOSFET [16], graphene FET transistors [17], MoS 2 FET [18], and CNTFET (Carbon NanoTube FET) [19], for use in design of analog and mixed circuits. Its major goal is to bring simple solutions, numerically efficient and close to the physics of the device.…”

Low-Temperature MoS2 Film Formation Using Sputtering and H2S Annealing

“…To overcome these problems, bottom-up processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), pulse laser deposition (PLD) and sputtering are required. The CVD, in which MoO 3 , sulfur powder, and hydrogen sulfide (H 2 S) are commonly used as precursors, is widely used because it allows us the synthesis of high-quality MoS 2 film on a sapphire substrate [10]- [16]. Although large-grain and high-quality MoS 2 film can be obtained, the deposition temperature is commonly high at 600 • C or more which is not appropriate for application such as 3D-monolithic ICs which require low thermal budget [17], [18].…”