MOS interface states: overview and physicochemical perspective

Abstract

The metal-oxide-semiconductor (MOS) transistor has become the dominant device for very large-scale integrated circuits. The performance and reliability of an MOS device are heavily influenced by the quality and properties of the interface between the oxide and the Si region directly beneath. Inherent, process-related, and operationally and environmentally generated interface states or traps are exceedingly harmful or disabling when present. Although controlled successfully by semiempirical design, fabrication and operational regimens, ever-smaller device size-approaching the scale in which a single trap can be important-makes further extension of knowledge on the basic physical and chemical aspects of interface states essential for confident technological progress. In addition, Si/SiO, interface states continue to merit research in their own right. This paper briefly highlights selected topics from past and present interface-state research, describes some essential physical and chemical properties, and introduces subjects to be covered in ensuing specialised papers.

Si (100)– SiO 2 interface properties following rapid thermal processing

“…24 In the case of a silicon ͑111͒ orientation, it is widely accepted to be a trivalent silicon center ("SiwSi 3 ) located at the interface, where the dangling bond is located perpendicular to the silicon/ oxide plane. 23 For the Si͑111͒-SiO 2 interface, the DOS distribution across the energy gap demonstrates two clear peaks in the lower and upper portions of the energy gap. The precise energy levels of the peaks in the DOS distribution vary slightly with the characterization method used.…”

“…Using the EPR method it has been shown that for unpassivated Si-SiO 2 interfaces the majority of the measured interface states are silicon atoms with dangling bond ( P b ) orbitals. 23 The technique most commonly used to dissociate the hydrogen from the Si-SiO 2 interfacial defects is vacuum annealing (1ϫ10 Ϫ6 Torr) at temperatures in the vicinity of 700°C. An alternative technique is to rapidly ͑Ͻ1 s͒ pull the wafers following a conventional furnace oxidation.…”

Генерация Поверхностных Электронных Состояний На Границе Раздела Кремний-Сверхтонкий Окисел В Процессе Полевого Повреждения Структур Металл-Окисел-Полупроводник

“…Исследования этих явлений для достаточно толстых (более 5 нм) слоев SiO 2 проводятся уже бо-лее 40 лет [2], и к настоящему времени развиты до-статочно полные представления о механизмах прояв-ляющихся эффектов [3][4][5][6]. Разработка наномасштабных электронных устройств стимулировала изучение повре-ждения тонких, и в особенности сверхтонких (толщиной менее 4 нм), изолирующих пленок.…”

Comment on “Reduction of interface-state density in 4H–SiC n-type metal–oxide–semiconductor structures using high-temperature hydrogen annealing” [Appl. Phys. Lett. 76, 1585 (2000)]

“…͑2͒ The energy spectrum of dangling-bond defects exhibits two peaks 4 ͑3͒ Subsequent to the passivation of dangling bonds with H, the reduction of the interface state density in the upper part of the semiconductor band gap ͑acceptors͒ should be equal to that of states in the lower part of the band gap ͑donors͒. Our experiments clearly show that this is not the case in SiC/SiO 2 , 2,3 while Fukuda et al present no data for p-type SiC.…”