MOS Capacitance Measurements for PEALD TiO2 Dielectric Films Grown under Different Conditions and the Impact of Al2O3 Partial-Monolayer Insertion

Abstract

In this paper, we report the plasma-enhanced atomic layer deposition (PEALD) of TiO2 and TiO2/Al2O3 nanolaminate films on p-Si(100) to fabricate metal-oxide-semiconductor (MOS) capacitors. In the PEALD process, we used titanium tetraisopropoxide (TTIP) as a titanium precursor, trimethyl aluminum (TMA) as an aluminum precursor and O2 plasma as an oxidant, keeping the process temperature at 250 °C. The effects of PEALD process parameters, such as RF power, substrate exposure mode (direct or remote plasma exposure) and Al2O3 partial-monolayer insertion (generating a nanolaminate structure) on the physical and chemical properties of the TiO2 films were investigated by Rutherford backscattering spectroscopy (RBS), Raman spectroscopy, grazing incidence X-ray diffraction (GIXRD), and field emission scanning electron microscopy (FESEM) techniques. The MOS capacitor structures were fabricated by evaporation of Al gates through mechanical mask on PEALD TiO2 thin film, followed by evaporation of an Al layer on the back side of the Si substrate. The capacitors were characterized by current density-voltage (J-V), capacitance-voltage (C-V) and conductance-voltage (G-V) measurements. Our results indicate that RF power and exposure mode promoted significant modifications on the characteristics of the PEALD TiO2 films, while the insertion of Al2O3 partial monolayers allows the synthesis of TiO2/Al2O3 nanolaminate with well-spaced crystalline TiO2 grains in an amorphous structure. The electrical characterization of the MOS structures evidenced a significant leakage current in the accumulation region in the PEALD TiO2 films, which could be reduced by the addition of partial-monolayers of Al2O3 in the bulk of TiO2 films or by reducing RF power.

Electrical Characterization of Positively Charged SiO Coatings for MOS Solar Cells

“…Figure 3a shows a physical circuit model that considers the capacitance of the MOS structure (CMOS) and the series resistance (RS) due to the silicon substrate and contacts. Moreover, Figure 3b corresponds to the circuit model of the measured capacitance (Cm) and conductance (Gm) extracted from commercial capacimeters to obtain the C-V and G-V characteristics [11][12][13]. Thus, the capacitance of the MOS structure and the series resistance can be obtained by matching the impedances of the two models in Figure 3.…”

“…. Circuit models of: (a) the MOS physical structure and (b) the measured parameters of a commecial capacimeter [12,13].…”

“…where Cma is the measured accumulation capacitance, Gma is the measured accumulation conductance and ω = 2πf (f = 1MHz). As a result, the relative permittivity of the dielectric (εr) is given by [11][12][13]:…”

“…where tox is the thickness of the gate oxide, AG is the gate area and ε0 is the vacuum permittivity constant (ε0 = 8.854x10 -14 F/cm). The effective charge density in the bulk of the gate oxide (Qf) is given by [11,12,14]:…”

“…where Si is the relative permittivity of the silicon substrate. The surface states density (Dit) of silicon oxide/silicon interfaces were estimated from the Hill-Coleman model for a single frequency measurement at the accumulation region as follows [12,16]:…”