In this paper we present an algorithm for standard-cell and gate array placement. This algorithm has been implemented as a part of TOPS -a layout synthesis package developed in the Institute of Informatics Systems. A new heuristics for standard cell placement was proposed that combines the features of iterative improvement with the ability to avoid gefflng stuck at local minima using a stochastic approach Our objective was to prevent the program from trapping at local minima on the one hand and to reduce CPU-time in comparing with simulated annealing on the other hand.