Monotonic Optimization of Dataflow Buffer Sizes

Hendriks, Martijn; Ara, Hadi Alizadeh; Geilen, Marc; Basten, Twan; Marin, Ruben Guerra; Jong, Rob N. de; Vlugt, Steven van der

doi:10.1007/s11265-018-1415-2

Cited by 5 publications

(3 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Same authors also proposed an iterative buffer sizing method [17,36] without needing for FSMs. Their input is still a pure CSDF [5] graph, and thus they benefit from dedicated throughput analysis methods to assert the throughput of each buffer size distribution.…”

Section: Sdf Analysis For Buffer Sizingmentioning

confidence: 99%

“…Moreover to accelerate our iterative method, PREESM benefits from the initial buffer size distribution computed with ADFG, and from the resource-wise optimization to reduce the number of iterations. Both techniques could be reused to accelerate the method in [17,36]. As their implementation is not open-source, we were not able to compare with it.…”

Section: Sdf Analysis For Buffer Sizingmentioning

confidence: 99%

See 1 more Smart Citation

Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow

Honorat,

Dardaillon,

Miomandre

et al. 2024

ACM Trans. Reconfigurable Technol. Syst.

View full text Add to dashboard Cite

High-Level Synthesis (HLS) tools are mature enough to provide efficient code generation for computation kernels on FPGA hardware. For more complex applications, multiple kernels may be connected by a dataflow graph. Although some tools, such as Xilinx Vitis HLS, support dataflow directives, they lack efficient analysis methods to compute the buffer sizes between kernels in a dataflow graph. This paper proposes an original method to safely approximate such buffer sizes. The first contribution computes an initial overestimation of buffer sizes, wihout knowing the memory access patterns of kernels. The second contribution iteratively refines those buffer sizes thanks to cosimulation. Moreover, the paper introduces an open source framework using these methods to facilitate dataflow programming on FPGA using HLS. The proposed methods and framework have been tested on 7 dataflow applications, and outperform Vitis HLS cosimulation in 5 benchmarks, either in terms of BRAM and LUT usage, or in term of exploration time. In the 2 other benchmarks, our best method gets results similar to Vitis HLS. Last but not least, our method admits directed cycles in the application graphs.

show abstract

Section: Sdf Analysis For Buffer Sizingmentioning

confidence: 99%

Section: Sdf Analysis For Buffer Sizingmentioning

confidence: 99%

Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow

Honorat,

Dardaillon,

Miomandre

et al. 2024

ACM Trans. Reconfigurable Technol. Syst.

View full text Add to dashboard Cite

show abstract

“…Although AXI has been a big help in standardizing hardware interfaces, it is still a primarily byte-oriented protocol developed for hardware designs, which means that 1) it is not very accessible for software developers and 2) custom glue logic is almost always necessary to integrate existing IP blocks into new designs or the other way around. As it turns out, the effort of creating glue logic, including for example arbitration and buffering (finding optimal buffer sizes in dataflow graphs is a research topic in itself [13]), is not to be underestimated.…”

Section: B Fpga Computingmentioning

confidence: 99%

FPGA Acceleration for Big Data Analytics: Challenges and Opportunities

Hoozemans

Peltenburg

Nonnemacher³

et al. 2021

IEEE Circuits Syst. Mag.

View full text Add to dashboard Cite

The big data revolution has ushered an era with ever increasing volumes and complexity of data requiring ever faster computational analysis. During this very same era, CPU performance growth has been stagnating, pushing the industry to either scale their computation horizontally using multiple nodes in datacenters, or to scale vertically using heterogeneous components to reduce compute time. However, networking and storage continue to provide both higher throughput and lower latency, which allows for leveraging heterogeneous components, deployed in data centers around the world. Still, the integration of big data analytics frameworks with heterogeneous hardware components such as GPGPUs and FPGAs is challenging, because there is an increasing gap in the level of abstraction between analytics solutions developed with big data analytics frameworks, and accelerated kernels developed with heterogeneous components. In this article, we focus on FPGA accelerators that have seen wide-scale deployment in large cloud infrastructures. FPGAs allow the implementation of highly optimized hardware architectures, tailored exactly to an application, and unburdened by the overhead associated with traditional general-purpose computer architectures. FPGAs implementing dataflow-oriented architectures with high levels of (pipeline) parallelism can provide high application throughput, often providing high energy efficiency. Latency-sensitive applications can leverage FPGA accelerators by directly connecting to the physical layer of a network, and perform data transformations without going through the software stacks of the host system. While these advantages of FPGA accelerators hold promise, difficulties associated with programming and integration limit their use. This article explores the existing practices in big data analytics frameworks, discusses the aforementioned gap in development abstractions, and provides some perspectives on how to address these challenges in the future.

show abstract