Molded chip scale package for high pin count

Baba, Shinji; Tomita, Yoshihiro; Matsuo, M.; Matsushima, H.; Ueda, N.; Nakagawa, O.S.

doi:10.1109/ectc.1996.550895

Cited by 17 publications

(3 citation statements)

References 8 publications

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“…Optimization of mold and DBF material and thickness will be required to manage on-die stress and the die level warpage performance. In addition, alternative bumping technologies [8][9][10] scalable to less than 0.3 mm pitch will be investigated as a lower cost option for high pin counts. Finally, we will need to define the minimum WLP thickness for handling and assembly using current surface mount infrastructure.…”

Section: Discussionmentioning

confidence: 99%

Wafer Level Packaging to Address Future Direct Chip Attach Needs

Tomita¹,

Sekihara²,

Kubota³

et al. 2012

Transactions of The Japan Institute of Electronics Packaging

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This paper covers results from early pathfinding investigations of a wafer level package (WLP) technology that addresses future direct chip attach (DCA) needs. An overview of the WLP technology and pathfinding results covering key process flow evaluations and future challenges to apply the concept to DCA are presented. Proof-of-concept (POC) of 300mm wafer-level mold integrating with Cu bumps was demonstrated by investigating the mold thickness uniformity, wafer warpage, and solder joint reliability on the board. We conclude with a discussion of the key risk areas remaining challenges that includes the mold grinding thickness variance control, optimization of the material properties, and alternative low cost bumping technologies scalable less than 0.3mm pitch, and outline the next steps to continue data collection on the wafer warpage behavior, the die breakage strength, and the board level assembly process using a standard surface mount infrastructure in our pathfinding work.

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Section: Discussionmentioning

confidence: 99%

Wafer Level Packaging to Address Future Direct Chip Attach Needs

Tomita¹,

Sekihara²,

Kubota³

et al. 2012

Transactions of The Japan Institute of Electronics Packaging

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“…It was found that the largest inelastic strain, creep strain energy density and von Mises stress always occurred at the upper-left corner of the 7th solder joint for both cases (refer to Figs. [7][8]. This is because the seventh solder joint has the largest distance from the neutral point (DNP).…”

Section: Stress Analysismentioning

confidence: 96%

“…In their studies, Yasunaga et al [7], [8] and Lall et al [9] adopted elasto-plastic constitutive relation for solder joints of CSP assemblies. Lau et al [10] used elastoplastic-creep constitutive relation for the solder joint.…”

Section: Introductionmentioning

confidence: 98%

Computational parametric analyzes on the solder joint reliability of bottom leaded plastic (BLP) package

Zhang

Lee

Choi

et al. 2002

IEEE Trans. Adv. Packag.

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The bottom-leaded plastic (BLP) package is a lead-on-chip type of chip scale package (CSP) developed mainly for the memory device. Because the BLP package is one of the smallest plastic packages available, solder joint reliability becomes a critical issue. In this study, a 28-pin BLP package is modeled to investigate the effects of molding compound and leadframe material properties, the thickness of printed circuit board (PCB), the shape of solder joint and the solder pad size on the board level solder joint reliability. A viscoplastic constitutive relation is adopted for the modeling of solder in order to account for its time and temperature dependence on thermal cycling. A three-dimensional nonlinear finite element analysis based on the above constitutive relation is conducted to model the response of a BLP assembly subjected to thermal cycling. The fatigue life of solder joint is estimated by the modified Coffin-Manson equation. The two coefficients in the modified Coffin-Manson equation are also determined. Parametric studies are performed to investigate the dependence of solder joint fatigue life on various design factors. Index Terms-BLP, CSP, finite element analysis, solder joint reliability, viscoplastic.

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Fan-in Wafer-Level Packaging Versus FOWLP

Lau

2018

Fan-Out Wafer-Level Packaging

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Molded chip scale package for high pin count

Cited by 17 publications

References 8 publications

Wafer Level Packaging to Address Future Direct Chip Attach Needs

Wafer Level Packaging to Address Future Direct Chip Attach Needs

Computational parametric analyzes on the solder joint reliability of bottom leaded plastic (BLP) package

Fan-in Wafer-Level Packaging Versus FOWLP

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