Module to perform multiplication, division, and square root in systolic arrays for matrix computations

Ercegovac, M.D.; Lang, T.

doi:10.1016/0743-7315(91)90045-b

Cited by 15 publications

(4 citation statements)

References 13 publications

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“…We now summarize the algorithm of the combined mcdule -mantissa part [5]. The range of the operands and results (mantissas only) is as shown in Table 1.…”

Section: The Algorithm Of the Combined Modulementioning

confidence: 99%

“…Moreover, since the results are produced in a digit-serial form, this form can be used in the communication among processors. performing the conversion to parallel form in the destination processor, as discussed further in [5]. During this conversion to parallel, the result is converted on-the-fly from redundant to conventional (2's complement or sign and magnitude) representation.…”

Section: Introductionmentioning

confidence: 99%

“…The presented module, based on the algorithm [5], is suitable for a floating-point representation of operands and results. In multiplication, the result corresponds to the most significant part of the product.…”

Section: Introductionmentioning

confidence: 99%

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Implementation of module combining multiplication, division, and square root

Ercegovac¹,

Lang²

IEEE International Symposium on Circuits and Systems

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The implementation of a module that performs radix-2 multiplication, division, and square mot is presented The module is compact because most of the components are s h a d by all three operations, the complexity being similar to a radix-2 divider. All three operations have the same execution time, one bit of the result is produced pcr cycle, beginning with the most significant bit. The cycle t i m e is kept small by the use of carry-save addition and result-digit selection based on a low-precision estimate of the partial remainder.The module incorporates on-the-fly conversion and rounding of the result.

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“…We now summarize the algorithm of the combined mcdule -mantissa part [5]. The range of the operands and results (mantissas only) is as shown in Table 1.…”

Section: The Algorithm Of the Combined Modulementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Implementation of module combining multiplication, division, and square root

Ercegovac¹,

Lang²

IEEE International Symposium on Circuits and Systems

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show abstract

“…Consequently, the implementations are not capable of accepting a new square root instruction on every clock cycle. A systolic array implementation is described in [3].…”

Section: Srt-redundant Methodsmentioning

confidence: 99%