Modular exponent realization on FPGAs

Põldre, Juri; Tammemäe, Kalle; Mandre, Marek

doi:10.1007/bfb0055261

Cited by 6 publications

(4 citation statements)

References 5 publications

(2 reference statements)

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“…In [4] it is argued that a systolic array needs more resources than the redundant approach to store the signals between the units in the array, but it is easier to route and can therefore be faster than a redundant representation on FPGAs. Poldre et al [13] also describe both approaches but did not implement them in hardware.…”

Section: Related Workmentioning

confidence: 95%

Accelerating the secure remote password protocol using reconfigurable hardware

Groen

Hämäläinen

Juurlink

et al. 2004

Proceedings of the 1st Conference on Computing Frontiers

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The Secure Remote Password (SRP) protocol is an authentication and key-exchange protocol suitable for secure password verification and session key generation over insecure communication channels. The modular exponentiations involved, however, are very time-consuming, causing slow logon procedures. This work presents the design of a hardware accelerator that performs modular exponentiation of very wide integers. The experimental platform is tutwlan, a Wireless Local Area Network (wlan) being developed at Tampere University of Technology. It runs on the Altera Excalibur development board that contains a microprocessor and a chip with programmable hardware. The results show that a full modular exponentiation with 1023-bit inputs can be performed in less than 40 ms using less than 10,000 logic elements, each consisting of a 4-input lookup table and a register. By using the implemented hardware accelerator in the authentication protocol, the execution time is reduced by a factor of 4. In addition, proposals to improve the implemented modular exponentiation architecture are presented. An additional factor of 5 improvement (totaling a factor of 20) can be achieved by implementing the fastest design.

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Section: Related Workmentioning

confidence: 95%

Accelerating the secure remote password protocol using reconfigurable hardware

Groen

Hämäläinen

Juurlink

et al. 2004

Proceedings of the 1st Conference on Computing Frontiers

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“…Considering modular exponentiation on FPGAs, more recent work include [156,21,22]. Elbirt and Paar evaluated some options in FPGA architecture suitable for PKC in [47].…”

Section: Systolic Arrays Based On Montgomery's Algorithmmentioning

confidence: 99%

Hardware architectures for public key cryptography

et al. 2003

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This paper presents an overview of hardware implementations for the two commonly used types of Public Key Cryptography, i.e. RSA and Elliptic Curve Cryptography (ECC), both based on modular arithmetic. We first discuss the mathematical background and the algorithms to implement these cryptosystems. Next an overview is given of the different hardware architectures which have been proposed in the literature.

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“…Efficient implementation of Montgomery modular multiplication (MMM) in hardware was considered by many authors [7,13,33,22,17,24,34,27,14,25,28].…”

Section: Introductionmentioning

confidence: 99%

Hardware implementation of an elliptic curve processor over GF(p) with Montgomery modular multiplier

Örs

Batina

Preneel

et al. 2008

IJES

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This paper describes a hardware implementation of an arithmetic processor which is efficient for bit-lengths suitable for both commonly used types of Public Key Cryptography (PKC), i.e., Elliptic Curve (EC) and RSA Cryptosystems. The processor consists of special operational blocks for Montgomery Modular Multiplication, modular addition/substraction, EC Point doubling/addition, modular multiplicative inversion, EC point multiplier, projective to affine coordinates conversion and Montgomery to normal representation conversion.

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Modular exponent realization on FPGAs

Cited by 6 publications

References 5 publications

Accelerating the secure remote password protocol using reconfigurable hardware

Accelerating the secure remote password protocol using reconfigurable hardware

Hardware architectures for public key cryptography

Hardware implementation of an elliptic curve processor over GF(p) with Montgomery modular multiplier

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