Modified Efficient Parallel Distributed Arithmetic based FIR Filter Architecture for ASIC and FPGA

Soni, Teena; Kumar, Arun; Panda, Manoj

doi:10.1109/spin57001.2023.10116765

Cited by 3 publications

(1 citation statement)

References 23 publications

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“…However, such implementations result in either low throughput per unit area or increased slice count 27,28 . In later works, 29–32 distributed arithmetic (DA)‐based implementations are reported but are not suited for ASIC implementation and result in higher slice count when implemented on FPGA 33 …”

Section: Review Of Recent Literature On Hardware Implementation Of Fi...mentioning

confidence: 99%

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Janwadkar,

Dhavse

2023

Circuit Theory & Apps

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The design of hand‐held portable devices for cardiovascular health monitoring based on the analysis of electrocardiogram (ECG) is a hot topic of research nowadays. Digital filters, possibly designed using digital multipliers, are a critical module in the design of such analysis systems. This paper presents the ASIC design of a 64th‐order digital low‐pass FIR filter to be used in ECG denoising applications. The FIR filter is optimized for usage in battery‐operated portable systems, wherein power consumption and on‐chip area are crucial parameters of concern. These challenges are met by employing a novel multiplier architecture, which we design by hybridizing the two popular digital multiplication algorithms, namely, the Vedic multiplication algorithm and the Wallace tree multiplication algorithm. The proposed multiplier consumes lower area and power consumption than either of the aforementioned conventional multiplication algorithms. This is established through FPGA‐based implementations on Artix‐7 FPGA, for the various wordlengths. The area and power optimizations are further exercised by two proposed techniques, namely, elimination of redundant multipliers, and power gating using the proposed zero‐detector circuit. RTL‐to‐GDSII flow has been completed using Cadence digital design and sign‐off tools for SCL 180 nm technology. The results indicate that the proposed filter architecture occupies 16.38% lower area and 79.58% lower power consumption than the contemporary designs described in the literature.

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Section: Review Of Recent Literature On Hardware Implementation Of Fi...mentioning

confidence: 99%

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Janwadkar,

Dhavse

2023

Circuit Theory & Apps

View full text Add to dashboard Cite

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Power and Delay-Efficient Matrix Vector Multiplier Units for the LSTM Networks Using Activity Span Reduction Technique and Recursive Adders

Joseph

Bindiya

2023

Circuits Syst Signal Process

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A hardware architecture design for interference rejection of ultrasound signals based on FPGA

Lin,

Chen,

2023

2023 International Conference on Computers, Information Processing and Advanced Education (CIPAE)

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Modified Efficient Parallel Distributed Arithmetic based FIR Filter Architecture for ASIC and FPGA

Cited by 3 publications

References 23 publications

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier

Power and Delay-Efficient Matrix Vector Multiplier Units for the LSTM Networks Using Activity Span Reduction Technique and Recursive Adders

A hardware architecture design for interference rejection of ultrasound signals based on FPGA

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