Modified Compressed Sparse Row Format for Accelerated FPGA-Based Sparse Matrix Multiplication

Pligouroudis, Michail; Nuno, Rafael Angel Gutierrez; Kázmierski, Tom J.

doi:10.1109/iscas45731.2020.9181266

Cited by 5 publications

(1 citation statement)

References 16 publications

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“…There are a variety of different formats in which only the nonzero values of a sparse matrix can be stored. Among these formats, Compressed Sparse Column (CSC) and CSR are two of the most commonly used and have inspired many variants (e.g., [23,24]). The Compressed Sparse Row (CSR) and CSC formats both store matrices efficiently without putting any restrictions on the contents of the matrix, whereas other formats may require the matrix to have certain sparsity pattern features such as symmetry, values being repeated multiple times, or store additional non-zeroes, such as sliced ELLPACK [15], to be efficient.…”

Section: Spmv Multiplicationmentioning

confidence: 99%

Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays

Hogervorst

Nane

Marchiori³

et al. 2021

ACM Trans. Reconfigurable Technol. Syst.

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Scientific computing is at the core of many High-Performance Computing applications, including computational flow dynamics. Because of the utmost importance to simulate increasingly larger computational models, hardware acceleration is receiving increased attention due to its potential to maximize the performance of scientific computing. Field-Programmable Gate Arrays could accelerate scientific computing because of the possibility to fully customize the memory hierarchy important in irregular applications such as iterative linear solvers. In this article, we study the potential of using Field-Programmable Gate Arrays in High-Performance Computing because of the rapid advances in reconfigurable hardware, such as the increase in on-chip memory size, increasing number of logic cells, and the integration of High-Bandwidth Memories on board. To perform this study, we propose a novel Sparse Matrix-Vector multiplication unit and an ILU0 preconditioner tightly integrated with a BiCGStab solver kernel. We integrate the developed preconditioned iterative solver in Flow from the Open Porous Media project, a state-of-the-art open source reservoir simulator. Finally, we perform a thorough evaluation of the FPGA solver kernel in both stand-alone mode and integrated in the reservoir simulator, using the NORNE field, a real-world case reservoir model using a grid with more than 10 5 cells and using three unknowns per cell.

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Section: Spmv Multiplicationmentioning

confidence: 99%

Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays

Hogervorst

Nane

Marchiori³

et al. 2021

ACM Trans. Reconfigurable Technol. Syst.

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Miniaturization for wearable EEG systems: recording hardware and data processing

2022

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As more people desire at-home diagnosis and treatment for their health improvement, healthcare devices have become more wearable, comfortable, and easy to use. In that sense, the miniaturization of electroencephalography (EEG) systems is a major challenge for developing daily-life healthcare devices. Recently, because of the intertwined relationship between EEG recording and processing, co-research of EEG recording hardware and data processing has been emphasized for whole-in-one miniaturized EEG systems. This paper introduces miniaturization techniques in analog-front-end hardware and processing algorithms for such EEG systems. To miniaturize EEG recording hardware, various types of compact electrodes and mm-sized integrated circuits (IC) techniques including artifact rejection are studied to record accurate EEG signals in a much smaller manner. Active electrode and in-ear EEG technologies are also researched to make small-form-factor EEG measurement structures. Furthermore, miniaturization techniques for EEG processing are discussed including channel selection techniques that reduce the number of required electrode channel and hardware implementation of processing algorithms that simplify the EEG processing stage.

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Multiple hierarchical compression for deep neural network toward intelligent bearing fault diagnosis

Sun

Liu

Wen

et al. 2022

Engineering Applications of Artificial Intelligence

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Modified Compressed Sparse Row Format for Accelerated FPGA-Based Sparse Matrix Multiplication

Cited by 5 publications

References 16 publications

Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays

Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays

Miniaturization for wearable EEG systems: recording hardware and data processing

Multiple hierarchical compression for deep neural network toward intelligent bearing fault diagnosis

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