versus conventional amorphous silicon TFTs, as well as large area processability at low temperatures. [13][14][15][16] Furthermore, MOTFTs are less affected by short channel effects. [17][18][19] As in other transistor technologies, MOTFT performance strongly depends on the intrinsic semiconductor channel properties as well as the channel interfacial characteristics, including that of the top surface. [20][21][22] Furthermore, MOTFTs are limited by uncontrollable back channel trap densities, restricting their application in high-resolution displays, as well as 3D and virtual reality devices. [7,[23][24][25][26][27] Recently, several strategies were reported to enhance the performance of MOTFTs by adopting new device architectures, including dual gate implantation, [28][29][30] high-k insulators, [31][32][33] and semiconducting heterostructures. [34][35][36][37][38] Among these strategies, low-dimensional bi-or multilayer heterostructures of different MOs have enhanced the carrier mobility and drive current in MOTFTs. [39,40] These improvements typically originate from confined free electrons within the potential well of the heterointerface between two semiconductors having large Fermi energy differences. [41] However, although these approaches are noteworthy, limitations in available component materials and control of leakage currents have compromised the fidelity of this platform. [37,38] Another approach to enhance performance Thin-film transistors using metal oxide semiconductors are essential in many unconventional electronic devices. Nevertheless, further advances will be necessary to broaden their technological appeal. Here, a new strategy is reported to achieve high-performance solution-processed metal oxide thin-film transistors (MOTFTs) by introducing a metallic micro-island array (M-MIA) on top of the MO back channel, where the MO is a-IGZO (amorphous indium-gallium-zinc-oxide). Here Al-MIAs are fabricated using honeycomb cinnamate cellulose films, created by a scalable breath-figure method, as a shadow mask. For IGZO TFTs, the electron mobility (µ e ) increases from ≈3.6 cm 2 V −1 s −1 to near 15.6 cm 2 V −1 s −1 for optimal Al-MIA dimension/ coverage of 1.25 µm/51%. The Al-MIA IGZO TFT performance is superior to that of controls using compact/planar Al layers (Al-PL TFTs) and Au-MIAs with the same channel coverage. Kelvin probe force microscopy and technology computer-aided design simulations reveal that charge transfer occurs between the Al and the IGZO channel which is optimized for specific Al-MIA dimensions/surface channel coverages. Furthermore, such Al-MIA IGZO TFTs with a high-k fluoride-doped alumina dielectric exhibit a maximum µ e of >50.2 cm 2 V −1 s −1 . This is the first demonstration of a micro-structured MO semiconductor heterojunction with submicrometer resolution metallic arrays for enhanced transistor performance and broad applicability to other devices.The ORCID identification number(s) for the author(s) of this article can be found under https://doi.org/10.1002/adma.202205871.
