Modern floorplanning based on fast simulated annealing

Abstract

Unlike classical floorplanning that usually handles only block packing to minimize silicon area, modern VLSI floorplanning typically needs to pack blocks within a fixed die (outline) and additionally considers the packing with block positions and interconnect constraints. Floorplanning with bus planning is one of the most challenging modern floorplanning problems because it needs to consider the constraints with interconnect and block positions simultaneously. We study in this paper two types of modern floorplanning problems:(1) fixed-outline floorplanning and (2) bus-driven floorplanning. Our floorplanner uses the B*-tree floorplan representation and is based on a fast three-stage simulated annealing scheme, called Fast-SA. For fixed-outline floorplanning, we present an adaptive Fast-SA that can dynamically change the weights in the cost function to optimize wirelength under the outline constraint. Experimental results show that our floorplanner can achieve almost 100% success rates efficiently for fixed-outline floorplanning with various aspect ratios, compared to 10%-90% success rates obtained by the most recent works. For the bus-driven floorplanning, we explore the feasibility conditions of the B*-tree with the bus constraints and develop a bus-driven floorplanning algorithm based on the conditions and Fast-SA. Experimental results show that our floorplanner on the average reduces 20% (55%) dead space for the floorplanning with hard (soft) macro blocks, compared with the most recent work. In particular, our floorplanner is more efficient than the previous works.

Benchmark Imagery for Assessing Geospatial Semantic Content Extraction Algorithms Final Report

“…To help do this, we wrote a computer tool to assist with creating facility layouts. Our approach was to adapt an existing computer code that automatically arranged electronic components on a circuit board, subject to a set of placement rules, B*-Tree Floorplanner [15]. The computer-generated facility layout specifications were passed to the synthetic scene generation software which, in turn, placed the components of the facility on the background and created a synthetic image.…”

“…One algorithm for performing automated layout is B*-Tree Floorplanner [15], which is readily available through the University of Michigan freeware package Parquet. [31] The algorithm is used for laying out electronic components and common lines (buses) in very large scale integrated (VLSI) circuits.…”

Voltage-Island Partitioning and Floorplanning Under Timing Constraints

“…A floorplan satisfies the floorplan-timing constraint if and only if, for each net whose source is block b i , the net length is less than or equal to o i , as derived in (4).…”

A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning

“…The reasons are twofold: 1) The B * -tree has been shown an efficient and effective data structure for floorplan design [2]; and 2) we intend to make fair comparison with the state-of-the-art multilevel-floorplanning work MB * -tree [13], which is also based on the B * -tree. The cost function Φ for SA is similar to the one in [20], and it is defined as follows:…”