Modelling run-time arbitration by latency-rate servers in dataflow graphs

Wiggers, Maarten H.; Bekooij, Marco; Smit, Gerard J. M.

doi:10.1145/1269843.1269846

Cited by 57 publications

(75 citation statements)

References 24 publications

(67 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Analysis can be performed manually, but formal verification is still useful for providing guarantees. Network calculus [26] has been demonstrated as a useful tool for NoC performance analysis [27]. However, it has limited applicability and precision for networks with backpressure and complex circular message dependencies.…”

Section: Related Workmentioning

confidence: 99%

Compositional Performance Verification of Network-on-Chip Designs

Holcomb

Seshia

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-This work presents a compositional approach to formally verify quality-of-service (QoS) properties of network-onchip (NoC) designs. A major challenge to scalability is the need to verify worst-case latency bounds for hundreds to thousands of cycles, which are beyond the capacity of state-of-the-art model checkers. The scalability challenge is addressed using a compositional model checking approach. The overall latency bound problem is divided into a number of smaller sub-problems, termed latency lemmas. The sub-problems imply the overall latency bound, but are easier to prove on account of being inductive. A method is presented for computing these lemmas based on the topology of the network and a subset of relevant state, and the latency lemmas are verified using k-induction. The effectiveness of this compositional technique is demonstrated on illustrative examples and an industrial ring interconnection network. In the ring network, a latency bound that cannot be verified in 10,000 seconds without lemmas is proved inductively in just 75 seconds when the lemmas are used.

show abstract

Section: Related Workmentioning

confidence: 99%

Compositional Performance Verification of Network-on-Chip Designs

Holcomb

Seshia

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…Again a value for σ needs to be found such that Equation (14) holds. We apply case distinction on n to find this value.…”

Section: Examplementioning

confidence: 99%

“…Our method does not have this restrictive oneto-one relation between firings and executions, instead we introduce a method that uses the modeling relation between dataflow components and tasks to capture the tasks workload functions. In [14] similar dataflow components as we use in this paper are used but the model from [14] also only allows to use one single (worst-case) execution time per task.…”

Section: Introductionmentioning

confidence: 99%

Two parameter workload characterization for improved dataflow analysis accuracy

Hausmans

Geuns

Wiggers

et al. 2013

2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS)

View full text Add to dashboard Cite

Abstract-Real-time stream processing applications, such as radios, can often be modeled intuitively with dataflow models. Given the Worst-Case Execution Times (WCETs) of the tasks, which characterizes workload with one parameter, dataflow analysis techniques have been used to compute the minimum throughput and maximum latency of these applications. However, a large difference between the WCETs of the tasks and their average execution times can result in a large difference between the computed worst-case throughput and the actual obtained throughput.To reduce the difference between the worst-case throughput, determined by analysis, and the actual obtained throughput, we introduce in this paper a two parameter (σ, ρ) workload characterization of the tasks to improve the accuracy of dataflow analysis. The (σ, ρ) workload characterization captures information on the maximum cumulative execution time of consecutive executions of a task and can therefore be seen as a generalization of the WCET characterization.We show how the (σ, ρ) workload characterization can be used in combination with several types of dataflow graphs and how it can be used to improve the temporal analysis results of real-time stream processing applications. We illustrate this for a DVB-T radio application, a car-radio application and a data-dependent MP3 playback application.

show abstract

“…For this purpose, a MATLAB module is written that models a simple SRAM memory controller with a 32-bit interface, both according to the latency-rate dataflow model of [28] and our new dataflow model, presented in Section V. Given a requested service curve, w ri , the module computes two lower bounds on the provided service curve, w ′ ri andw ′ ri , based on the latency-rate and the bi-rate dataflow models, respectively. The experiment setup is illustrated in Figure 9, where the execution duration of actor S ri of the LR server model is given by χ(S ri ) = 1/ρ A requested service curve w is generated by tracing memory transactions of a real-life application.…”

Section: A Experimental Setupmentioning

confidence: 99%

“…Modeling resource sharing with dataflow components is not trivial, as equivalence in temporal behavior with the service guarantees of the arbiters should be proved using rigorous algebraic steps [26], [27]. In [28], a general dataflow model for arbiters in the class of LR servers is presented that also covers CCSP. However, the basis of this dataflow model is the current linear LR service guarantee, and hence suffers from the associated over-allocation problem for priority-based arbiters.…”

Section: Introductionmentioning

confidence: 99%

Resource-Efficient Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration

Siyoum

Åkesson

Stuijk

et al. 2011

2011 IEEE 17th International Conference on Embedded and Real-Time Computing Systems and Applications

View full text Add to dashboard Cite

Abstract-A present-day System-on-Chip (SoC) runs a wide range of applications with diverse real-time requirements. Resources, such as processors, interconnects and memories, are shared between these applications to reduce cost. Resource sharing causes temporal interference, which must be bounded by a suitable resource arbiter. System-level analysis techniques use the service guarantee of the arbiter to ensure that realtime requirements of these applications are satisfied. A service guarantee that underestimates the minimum service provided by an arbiter results in more allocation of resources than needed to satisfy latency and throughput requirements. For instance, a linear service guarantee cannot accurately capture bursty service provision by many priority-based schedulers, such as Credit-Controlled Static Priority (CCSP) and Priority-Budget Scheduling (PBS). As a result, the timing analysis of these arbiters becomes too pessimistic. This leads to unnecessary cost penalties since some SoC resources, such as SDRAM bandwidth, are scarce and expensive.

show abstract

Modelling run-time arbitration by latency-rate servers in dataflow graphs

Cited by 57 publications

References 24 publications

Compositional Performance Verification of Network-on-Chip Designs

Compositional Performance Verification of Network-on-Chip Designs

Two parameter workload characterization for improved dataflow analysis accuracy

Resource-Efficient Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration

Contact Info

Product

Resources

About