Modelling and Validating a multiple-configuration railway signalling system using SDL

Fantechi, Alessandro; Spinicci, Emilio

doi:10.1016/s1571-0661(04)81026-0

Cited by 4 publications

(4 citation statements)

References 2 publications

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“…In particular some first experiments, have been attempted, modeling in SDL some already produced systems [1,7], with specific attention to the issues of validation coverage [2] and of code generation [3].…”

Section: The Experimentsmentioning

confidence: 99%

A Story About Formal Methods Adoption by a Railway Signaling Manufacturer

Bacherini

Fantechi

Tempestini

et al. 2006

FM 2006: Formal Methods

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Abstract. This paper reports the story of the introduction of formal methods in the development process of a railway signaling manufacturer. The first difficulty for a company is due to the many different formal methods proposals around; we show how this difficulty has been addressed and how the choice of a reference formal specification notation and of the related tools has been driven by many external factors related to the specific application domain, to the company policies, to european regulations. Cooperation with University has been fundamental in this process, which is now at the stage in which internal acceptance of the chosen formalisms and tools is established.

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Section: The Experimentsmentioning

confidence: 99%

A Story About Formal Methods Adoption by a Railway Signaling Manufacturer

Bacherini

Fantechi

Tempestini

et al. 2006

FM 2006: Formal Methods

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“…If failure has occurred, the DIAGNOSTIC block will notify the LOOP MAIN to lead the system to a fail-safe state by sending all the processes a suitable reset signal. We refer to [14,15] for a more detailed description of the system and its SDL specification. To generate the C code, the SDL system has been reengineered avoiding some SDL constructs, such as FPARS, for process creation with parameters, and Continuous Signals, accordingly to Cmicro code generator restrictions.…”

Section: Railway Signalling Systemmentioning

confidence: 99%

A comparison between handwritten and automatic generation of C code from SDL using static analysis

Becucci

Fantechi

Giromini³

et al. 2005

Softw: Pract. Exper.

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The experience reported in this paper relates to an evaluation of the automatic generation of C code from the Specification and Description Language (SDL) specification of embedded applications. The evaluation has been carried out by comparing the automatically generated code with the manually implemented code, both compliant to the same SDL specification: this comparison is based on a selection of metrics measured on both codes by means of commercial static analysis tools. Notwithstanding the different structure of the two codes, we appropriately selected and aggregated the obtained results in order to use them as indicators of code size, control flow complexity and integration flow complexity. For a better comparison of the two codes, we have also introduced a novel complexity metric, which compares the control flow complexity with the integration flow of the two different software architectures. The aim of the paper is not merely to evaluate the code generator used, but rather to propose a set of techniques that can be used to conduct similar evaluations.

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“…QUACK refined and extended the method, and evaluated the results by analyzing the SCA system (Sistema Conta Assi, axes counter system), described in [15]. SCA is a railway signaling device used to decide if a given railway section is free or still occupied by a train.…”

Section: Verification Of Non Functional Propertiesmentioning

confidence: 99%

“…An elaboration of the model described in [15] is presented in this volume in the paper by Banci et al [4].…”

Section: Verification Of Non Functional Propertiesmentioning

confidence: 99%

QUACK: A Platform for the Quality of New Generation Integrated Embedded Systems

Pezzè¹,

Baldini²,

Denaro³

et al. 2005

Electronic Notes in Theoretical Computer Science

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Over the last two years, the QUACK project investigated a new methodology for assessing the quality of heterogeneous, modular and configurable embedded systems, i.e., systems made out of a number of hardware and software components, usually embedded in devices with real-time requirements, and produced in families of different versions and configurations. The main aim of the project was to overcome the limitations of traditional techniques in dealing with the many new aspects and issues that arise, when the addressed class of systems is under concern. This paper surveys the final results of the QUACK project: that is, a new methodology for quality assessment of heterogeneous, modular and configurable embedded systems, throughout the whole software process.

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Modelling and Validating a multiple-configuration railway signalling system using SDL

Cited by 4 publications

References 2 publications

A Story About Formal Methods Adoption by a Railway Signaling Manufacturer

A Story About Formal Methods Adoption by a Railway Signaling Manufacturer

A comparison between handwritten and automatic generation of C code from SDL using static analysis

QUACK: A Platform for the Quality of New Generation Integrated Embedded Systems

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