Modelling and optimising run-time reconfigurable systems

Luk,; Shirazi,; Cheung, Vien

doi:10.1109/fpga.1996.564815

Cited by 55 publications

(15 citation statements)

References 10 publications

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“…An alternative to run-time bit-stream reconfiguration is based on using multiplexers and demultiplexers for time multiplexing designs [6,11,20]. This method supports fast reconfiguration but requires a large area.…”

Section: Related Workmentioning

confidence: 99%

“…Previously we reported a model [11] and the associated development tools [12] for reconfigurable designs. In this model, a component that can be configured to behave either as A or as B is described by a network with A and B connected between two control blocks.…”

Section: Multiplexer-based Reconfigurationmentioning

confidence: 99%

“…Each control block can then be mapped either into a real multiplexer or demultiplexer to form a single-cycle reconfigurable design, or into virtual ones which model the control mechanisms for replacing one configuration by another [11].…”

Section: Multiplexer-based Reconfigurationmentioning

confidence: 99%

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Reconfigurable design with clock gating

Osborne¹,

Luk²,

Coutinho³

et al. 2008

2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

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This paper describes an approach for developing energyoptimized run-time reconfigurable designs which benefit from clock gating. The approach is applied to two techniques: multiplexer-based reconfiguration, and reconfigurable wordlength optimization. The conditions under which this approach would be preferable to bit-stream reconfiguration are derived. Various case studies, such as ray tracing, guitar string simulation and matrix-vector multiplication, are used to illustrate this approach.

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Section: Related Workmentioning

confidence: 99%

Section: Multiplexer-based Reconfigurationmentioning

confidence: 99%

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Reconfigurable design with clock gating

Osborne¹,

Luk²,

Coutinho³

et al. 2008

2008 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

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“…Additional features support writing many words of configuration memory with the same data simultaneously (to reduce configuration time) and grouping nonadjacent registers within the user design into a single word for transfer to and from the processor. XC6200 application development and debug is supported by the XACTStep Series 6000 CAD software package and by a PCI bus resident development system [2]. The XC6200 architecure is derived from the Algotronix CAL technology which Xilinx aquired in 1992 [3] [4].…”

Section: Introductionmentioning

confidence: 99%

A fast constant coefficient multiplier for the XC6200

Kean

New

Slous

1996

Lecture Notes in Computer Science

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Abstract. We discuss the design of a high performance constant coefficient multiplier on the Xilinx XC6200 FPGA. The dynamic reconfiguration capabilities of the device are used to allow the constant coefficient to be rapidly changed. The design also provides better performance and density than similar multipliers on state of the art conventional FPGA's which require complete reconfiguration to change the coefficient.

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“…al reported in [12] and to a lesser extent in [13]. The dynamic selection scheme we present here is a little more general than Luk's RC_MUX mechanism, which requires all the alternatives to have inputs of the same type and an output of the same type (at the bit level) as shown in Figure 3.…”

Section: Dynamic Selectionmentioning

confidence: 94%

Interface specification for reconfigurable components

Singh¹

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.

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This paper presents a way of encoding some kinds of dynamic reconfiguration behaviour in the interface portion of circuit descriptions. This has many advantages. The user of a reconfigurable circuit has some knowledge about the reconfigurable interface of the circuit. Static analysis tools can make better decisions about how to schedule virtual hardware. And most importantly the compiler can automatically synthesize the required interface between reconfigurable portions of the system and the regular portions of the design. Several existing models of dynamic reconfiguration from the literature are captured using our type system extension based on sum types. This is especially important in System-on-Chip (SoC) contexts where a reconfigurable IP block may have to communicate over a non-trivial IP bus like CoreConnect TM .

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Modelling and optimising run-time reconfigurable systems

Cited by 55 publications

References 10 publications

Reconfigurable design with clock gating

Reconfigurable design with clock gating

A fast constant coefficient multiplier for the XC6200

Interface specification for reconfigurable components

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