Modelling and Characterisation of Fractal Based RF Inductors on Silicon Substrate

Marić, Andrea; Radosavljevic, Goran; Živanov, M.; Živanov, Ljiljana; Stojanović, Goran; Mayer, Martin; Jachimowicz, A.; Keplinger, Franz

doi:10.1109/asdam.2008.4743314

Cited by 11 publications

(11 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…When this trend is compared with other fractal geometries, for example, the Hilbert fractal of [20] and [21], which has a meander configuration as its second-order structure, from second order to fifth order, both the inductance and effective area occupied increased five times, where for the loop base structure studied here to the third order, the inductance improved 9.9 times while essentially maintaining the same occupied space. These structures also compare favorably to the extensive study in [1] when normalized for electrode thicknesses.…”

Section: Effect Of Fractalizationmentioning

confidence: 72%

Fractal Loop Inductors

Shoute

Barlage

2015

IEEE Trans. Magn.

View full text Add to dashboard Cite

We report a significant fractal-scaled increase in inductance for conductive pathways oriented in a fractal loop-based layout for a suite of planar inductors, which effectively occupy the same layout space and require only a single fabrication layer. These are closely predicted using a fractal scaling model for generalized loop-based inductors elucidated in this paper. Single-layer planar fractal structures were investigated with the loop inductor serving as the base construct. Thin sub-200 nm Cr/Au metal films compatible with flexible and stretchable substrates were used. It was found that while higher fractal orders did improve the inductive performance (over nine times from zeroth to third order), it is met with increased resistance. However, when compared with its equivalent series orientation, the effective sheet resistance of the simple fractal strategy demonstrated a clear advantage of up to four times. When the inductor is normalized for thickness, a quality factor Q greater than 40 is observed for all structures. Finally, the inductance quality gain figure of merit showing the optimal geometrical approach is introduced to quantify the quality of the structure's inductance over its resistance.

show abstract

Section: Effect Of Fractalizationmentioning

confidence: 72%

Fractal Loop Inductors

Shoute

Barlage

2015

IEEE Trans. Magn.

View full text Add to dashboard Cite

show abstract

“…In contrast, conventional planar inductors require a large on-chip area to achieve high inductance values. Fractal geometry-based inductors act as a feasible solution to achieve higher inductance due to longer trace lengths [2][3][4]. The conventional series stacked fractal inductor (CSSFI) improves the inductance and self-resonance frequency ( f SR ) and reduces the quality factor (Q) [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Design of a high performance narrowband low noise amplifier using an on-chip orthogonal series stacked differential fractal inductor for 5G applications

Tumma¹,

Nistala²

2020

Turk J Elec Eng & Comp Sci

View full text Add to dashboard Cite

Inductors play a crucial role in the design of radio frequency integrated circuits (RFICs) and they typically consume a considerably large area and have a low-quality factor at high frequencies.The employment of fractal structure in on-chip inductors helps in improving the quality factor and also reduces the overall area besides improving the inductance value. In this paper, an orthogonal series stacked differential fractal inductor is proposed and the same is used to design a low noise amplifier (LNA) for 5G band (27-30 GHz) applications. The proposed inductor is fabricated on a multilayer printed circuit board and the measurement results demonstrate twice the enhancement in inductance, 56% improvement in quality factor, and 33% reduction in series resistance when compared to the conventional series stacked fractal inductor for the equivalent on-chip area. The LNA using cascode topology with inductive source degeneration is designed and simulated at a center frequency of 28 GHz in 90 nm CMOS technology using the tool Advanced Design System. The inductors in the LNA are replaced with the proposed on-chip inductor for different layers, which contributes to high gain, better input matching, and low noise figure compared to the state-of-the-art LNAs.

show abstract

“…Therefore, relevant option is not conducive for applications in systems like smart-phones and other handheld devices encountering restricted space. Alternative to bulk solenoidal inductors, advocated in practice for space-constrained circuit-board applications is planar geometry of copper-traces (such as spiral traces) designed to emulate the desired inductance values [3] [4].…”

Section: Introductionmentioning

confidence: 99%

Mitigating Time Interval Error (TIE) in High-Speed Baseband Digital Transports: Design for Delay Compensation at Baseband Infrastructure of Smart-Phones Using Fractal Dispersive Delay-Lines

Neelakanta¹,

Noori²

2014

View full text Add to dashboard Cite

A major concern in modern smart-phones and hand-held devices is a way of mitigating the time interval error (TIE) perceived at high-speed digital transits along the traces of the circuit-board (rigid and or flexible) used in baseband infrastructures. Indicated here is a way of adopting a planar fractal inductor configuration to improvise the necessary time-delay in the transits of digital signal phase jitter and reduce the TIE. This paper addresses systematic design considerations on fractal inductor geometry commensurate with practical aspects of its implementation as delaylines in the high-speed digital transports at the baseband operations of smart-phone infrastructures. Experimental results obtained from a test module are presented to illustrate the efficacy of the design and acceptable delay performance of the test structure commensurate with the digital transports of interest.

show abstract

Modelling and Characterisation of Fractal Based RF Inductors on Silicon Substrate

Cited by 11 publications

References 2 publications

Fractal Loop Inductors

Fractal Loop Inductors

Design of a high performance narrowband low noise amplifier using an on-chip orthogonal series stacked differential fractal inductor for 5G applications

Mitigating Time Interval Error (TIE) in High-Speed Baseband Digital Transports: Design for Delay Compensation at Baseband Infrastructure of Smart-Phones Using Fractal Dispersive Delay-Lines

Contact Info

Product

Resources

About