Modeling, Verification, and Signal Integrity Analysis of High-Speed Signaling Channel with Tabbed Routing in High Performance Computing Server Board

Song, Ki-Il; Kim, Jong-Wook; Kim, Hyun-Woong; Lee, Seonghi; Ahn, Jangyong; Brito, Andres; Kim, Hyun-Sik; Park, Min‐Ho; Ahn, Seungyoung

doi:10.3390/electronics10131590

Cited by 7 publications

(6 citation statements)

References 5 publications

(16 reference statements)

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“…The vertical tabbed via can mitigate the influence of far-end crosstalk between vertical channels. This effect is similar to the effect of reducing far-end crosstalk by increasing mutual capacitance, such as tabbed routing mainly used in the breakout zone of PCBs [ 12 , 13 ]. The physical dimension and electrical properties are summarized in Table 1 .…”

Section: Proposal and Modeling Of The Broadside Interposer Channel St...mentioning

confidence: 70%

A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory

et al. 2022

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In this paper, we propose and analyze a novel interposer channel structure with vertical tabbed vias to achieve high-speed signaling and low-power consumption in high-bandwidth memory (HBM). An analytical model of the self- and mutual capacitance of the proposed interposer channel is suggested and verified based on a 3D electromagnetic (EM) simulation. We thoroughly analyzed the electrical characteristics of the novel interposer channel considering various design parameters, such as the height and pitch of the vertical tabbed via and the gap of the vertical channel. Based on the frequency-dependent lumped circuit resistance, inductance, and capacitance, we analyzed the channel characteristics of the proposed interposer channel. In terms of impedance, insertion loss, and far-end crosstalk, we analyzed how much the proposed interposer channel improved the signal integrity characteristics compared to a conventional structure consisting of micro-strip and strip lines together. Compared to the conventional worst case, which is the strip line, the eye-width, the eye-height, and eye-jitter of the proposed interposer channel were improved by 17.6%, 29%, and 9.56%, respectively, at 8 Gbps. The proposed interposer channel can reduce dynamic power consumption by about 28% compared with the conventional interposer channel by minimizing the self-capacitance of the off-chip channel.

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Section: Proposal and Modeling Of The Broadside Interposer Channel St...mentioning

confidence: 70%

A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory

et al. 2022

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“…Song et al, Liu et al, and Wu et al. respectively used the segmentation approach [7] [8] and viable wide-band circuit model [9] methods to analyze NUTL. Cai et al added graphene paraffin material to the signal line with labels to suppress FEXT [10] and increased the cost of batch production.…”

Section: Introductionmentioning

confidence: 99%

Design of T-shaped non-uniform microstrip lines for reducing crosstalk in high-speed PCBs

Dong,

Duan,

Xie

2023

J. Phys.: Conf. Ser.

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High-speed and high-density PCB circuit layout design faces serious signal integrity problems. Crosstalk is one of the key problems affecting signal quality. Periodic non-uniform differential microstrip lines have the possibility of reducing crosstalk. This paper proposes a T-shaped non-uniform microstrip line, which adds the T-shaped bump on the inner side of the parallel microstrip lines. The microstrip line adopts the minimum batch production process linewidth to maintain high density, which is suitable for occasions where the line spacing is three times the linewidth. The principle of crosstalk mitigation for T-shaped microstrip lines is explained, and the evolution process of T-shaped microstrip lines is given, compared with parallel microstrip lines and tabbed lines with the same density. The simulation resulting in the time domain and frequency domain shows that the transmission performance of the T-shaped microstrip line is good, and crosstalk can be effectively suppressed in a high-frequency band, even better in some specific frequencies due to the crosstalk fluctuation with frequency.

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“…The assessment of signal integrity and power integrity (SiPI) of mixed signal interconnected digital input-output (IO) link aims to simulate the impairments of the channel and power delivery network (PDN), respectively. Therefore, it is important to explore SiPI assessment at different process, voltage, and temperature (PVT) corners of the designed IO link in order to ensure a good quality of the signal propagating on the package and printed circuit board (PCB) interconnects, hence a robust IO link design [1][2][3]. In fact, several industries (e.g., automotive, aerospace, consumer electronics) are driving the need for power integrity and PDN analysis due to the high density of multichip design and the massive high-speed data processing requiring fast DDR memory, server CPU, and multi-level signaling with low-level power rail voltages for power saving [2,3].…”

Section: Introductionmentioning

confidence: 99%

“…and the massive high-speed data processing requiring fast DDR memory, server CPU, and multi-level signaling with low-level power rail voltages for power saving [2,3]. Timing and amplitude distortions of the signals (i.e., currents and voltages) are not only due to channel design, such as inter-symbol interference, reflection, and crosstalk between lines, but can also be induced by the power and ground supply voltage (PGSV) variations at the die level.…”

Section: Introductionmentioning

confidence: 99%

“…The device's switching currents in the last stage (e.g., i H (t) and i L (t)) and pre-driver stage (e.g., i H p (t) and i Lp (t)), flowing via the PDN, produce the PGSV variations, generating the timing distortions at the output voltage, which is defined by the P/G supply-induced jitter (PGSIJ) [7]. and the massive high-speed data processing requiring fast DDR memory, server CPU, and multi-level signaling with low-level power rail voltages for power saving [2,3]. Timing and amplitude distortions of the signals (i.e., currents and voltages) are not only due to channel design, such as inter-symbol interference, reflection, and crosstalk between lines, but can also be induced by the power and ground supply voltage (PGSV) variations at the die level.…”

Section: Introductionmentioning

confidence: 99%

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Analysis of Pre-Driver and Last-Stage Power—Ground-Induced Jitter at Different PVT Corners

Souilem

Melício

Dghais

et al. 2022

Sensors

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This paper presents the study of power/ground (P/G) supply-induced jitter (PGSIJ) on a cascaded inverter output buffer. The PGSIJ analysis covers the IO buffer transient simulation under P/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct P/G DC supply voltages at the pre-driver (i.e., VDD/VSS) and last stage (i.e., VDDQ/VSSQ). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input–output buffer information specification (IBIS)-like model. Accordingly, the measured PGSIJ depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver’s technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSIJ) induced by both the driver’s IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions.

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Modeling, Verification, and Signal Integrity Analysis of High-Speed Signaling Channel with Tabbed Routing in High Performance Computing Server Board

Cited by 7 publications

References 5 publications

A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory

A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory

Design of T-shaped non-uniform microstrip lines for reducing crosstalk in high-speed PCBs

Analysis of Pre-Driver and Last-Stage Power—Ground-Induced Jitter at Different PVT Corners

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