Modeling the threshold voltage of core-and-outer gates of ultra-thin nanotube Junctionless-double gate-all-around (NJL-DGAA) MOSFETs

Kumar, Nitish; Purwar, Vaibhav; Awasthi, Himanshi; Gupta, Rajeev; Singh, Kunal; Dubey, Sarvesh

doi:10.1016/j.mejo.2021.105104

Cited by 24 publications

(3 citation statements)

References 30 publications

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“…The density gradient model is used in a simulation that deals with the quantum confinement effect in the narrow channel region. Quantum confinement becomes significant when channel thickness of the device is downscaled [13,33]. Schrodinger's equation is solved for the quantization energy error correction [13].…”

Section: Model Calibration and Simulation Setupmentioning

confidence: 99%

“…Quantum confinement becomes significant when channel thickness of the device is downscaled [13,33]. Schrodinger's equation is solved for the quantization energy error correction [13]. Thermal conductivity is kept less than the drain/source region in the nanotube due to phonon boundary scattering and dynamic quantum confinement effects [34,35].…”

Section: Model Calibration and Simulation Setupmentioning

confidence: 99%

“…However, the junctionless silicon-nanotube (Si-NT) FET is more suitable for the 3 nm technology nodes [10] due to its excellent immunity to SCEs. This immunity of SCEs arises due to uniform doping concentration throughout the source-channel-drain region [11][12][13].…”

Section: Introductionmentioning

confidence: 99%

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Impact of ambient temperature and thermal resistance on device performance of junctionless silicon-nanotube FET

2022

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In this article, a comprehensive analysis of the impact of electrothermal characteristics in the junctionless silicon-nanotube (Si-NT) field-effect-transistors (FETs) is carried out using the Sentaurus TCAD. The combined study of the variation in thermal contact resistance (1×10-9 to 1×10-8 m2W/K), ambient temperature (300K to 400K), and spacer length (5nm to 20nm) are performed. Significant improvements are observed in carrier temperature by 14%, lattice temperature by 13.7%, and gate leakage current from 0.787nA to 0.218fA due to the change in the spacer length. Further, a change in the drain current of 27.36% for thermal resistance (Rth) and of 11.62% due to ambient temperature is observed. We also show that the junctionless device suffers significantly less from self-heating effects because of the electric field intensity, which is much lower in the channel region.

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Section: Model Calibration and Simulation Setupmentioning

confidence: 99%