Modeling the switching behaviour of SuperJunction MOSFETs in cascode configuration with a low voltage silicon MOSFET

2016 IEEE Energy Conversion Congress and Exposition (ECCE)

Castro

et al. 2016

Self Cite

Abstract-This paper evaluates the SuperJunction MOSFET in cascode configuration with a low-voltage silicon MOSFET. The structure combines the good switching performance provided by the cascode configuration with advantages of the silicon technology as the robustness, the maturity and the low-cost. The objective of this paper is to elucidate and to demonstrate the reduction of switching losses of SuperJunction MOSFETs in cascode configuration with respect to their standalone counterparts (directly driven). A detailed simulation analysis of power loss contributions is carried out under hard-switching operation. Eventually, experimental evidence is provided by using a boost converter (100 V-to-400 V) in continuous conduction mode for a wide range of switching frequency (100 kHz-to-400 kHz) and output power (180W-to-500W).

Section: B Brief Description Of Turn-on and Turn-off Transitionsmentioning

confidence: 99%

“…The schematic circuit proposed in [14] is shown in Fig. 3 to explain the behaviour of the SJ-CC during the turn-on and turnoff.…”

Section: B Brief Description Of Turn-on and Turn-off Transitionsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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SuperJunction cascode, a configuration to break the silicon switching frequency limit

2016 IEEE Energy Conversion Congress and Exposition (ECCE)

Castro

et al. 2016

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“…The use of a SJ-FET in CC with a LV-FET (SJ-CC) was firstly proposed to reduce switching losses in [11]- [12]. A theoretical model of the switching mechanism during forward conduction of SJ-CCs paying especial attention to critical Improving the Third Quadrant Operation of Superjunction MOSFETs by Using the Cascode Configuration parasitic elements can be found in [13]. Moreover, it was demonstrated that the SJ-CC can outperform the SJ-FET in standalone configuration when the switching frequency is in the order of hundreds of kHz and operating under hard-switching and high-forward current conditions [14]- [15].…”

Section: Introductionmentioning

confidence: 99%

Improving the Third Quadrant Operation of Superjunction MOSFETs by Using the Cascode Configuration

IEEE Trans. Power Electron.

Lamar

Roig

et al. 2019

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In this paper, the third quadrant behavior of a High-Voltage (HV) Superjunction MOSFET (SJ-FET) in Cascode Configuration (CC) with a Low-Voltage silicon MOSFET (LV-FET) is deeply studied by means of an analytical model and experimental data. The third quadrant dynamic behavior of the SJ-CCs is compared to the standalone counterparts by evaluating their reverse recovery time (tRR), reverse recovery peak current (IRRM) and reverse recovery charge (QRR). An analytical model and experimental results show that the SJ-CC avoids or mitigates the activation of the SJ-FET body-diode during the third quadrant operation. As a consequence, the SJ-CC strongly improves the widely used Figure-of-Merit (FoM) RON·QRR, which considers the on-state resistance of the transistors ( RON). In addition, the results obtained using a SJ-CC are similar or better than the achieved by SJ-FETs with enhanced reverse recovery (i.e., irradiated SJ-FETs). This paper also includes a comparison with commercial wide bandgap switches, concluding that the RON·QRR value provided by the SJ-CC is around eight times higher than the provided by a commercial GaN cascode.

“…Using the proposed circuit the turn-On and the turn-OFF transitions of the cascode topology will be briefly explained. A more detailed analysis of this process can be found in [8].…”

Section: Structurementioning

confidence: 99%

Switching performance comparison of a power switch in a cascode configuration using a SuperJunction MOSFET

Lopez

2016 51st International Universities Power Engineering Conference (UPEC)

Rogina

et al. 2016

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Abstract-This paper is focused on the analysis of the cascode connection of Superjunction MOSFETs (SJ-FET) working as a high voltage normally-off power switch, based on Silicon technologies. In order to carry out this analysis, it will compare the cascode structure with the standalone connection, in which only one SJ-FET is used. The comparison is carried out in terms of switching behaviour, in order to verify if the cascode has a faster switching than a directly controlled SJ-FET. Experimental measurements are presented for both topologies working on a boost converter with an input voltage of 150 V, output voltage of 400 V, power range between 100 W and 400 W and a switching frequency range between 100 kHz and 400 kHz. Finally, an analysis of losses on the boost converter for both topologies is included.