Modeling the Memory of the Cray2 for Compile Time Optimization

Abstract

In a previous work [3], a cyclic scheduling method was shown efficient to generate vector code for the Cray-2 architecture, and compared to existing compilers. This method was using the framework of microcode compaction through a simplified model of the Cray-2 vector instruction stream. In this paper, we further elaborate on how to model the machine architecture within the underlying cyclic scheduling method. The impact of the choice of the model on the code generated is analyzed and performance results are presented.