Modeling Stray Capacitances of High-Voltage Capacitive Dividers for Conventional Measurement Setups

Abstract

Stray capacitances (SCs) are a serious issue in high-voltage (HV) applications. Their presence can alter the circuit or the operation of a device, resulting in wrong or even disastrous consequences. To this purpose, in this work, we describe the modeling of SCs in HV capacitive dividers. Such modeling does not rely on finite element analysis or complicated geometries; instead, it starts from an equivalent circuit of a conventional measurement setup described by the standard IEC 61869-11. Once the equivalent model including the SCs is found, closed expressions of the SCs are derived starting from the ratio error definition. Afterwards, they are validated in a simulation environment by implementing various circuit configurations. The results demonstrate the expressions applicability and effectiveness; hence, thanks to their simplicity, they can be implemented by system operators, researchers, and manufacturers avoiding the use of complicated methods and technologies.

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