Modeling Short-Range Microwave Networks to Scale Superconducting Quantum Computation

Abstract

A core challenge for superconducting quantum computers is to scale up the number of qubits in each processor without increasing noise or cross-talk. Distributing a quantum computer across nearby small qubit arrays, known as chiplets, could solve many problems associated with size. We propose a chiplet architecture over microwave links with potential to exceed monolithic performance on near-term hardware. We model and evaluate the chiplet architecture in a way that bridges the physical and network layers. We find concrete evidence that distributed quantum computing may accelerate the path toward useful and ultimately scalable quantum computers. In the long-term, short-range networks may underlie quantum computers just as local area networks underlie classical datacenters and supercomputers today.

Noisy intermediate-scale quantum computers

“…In the future, we may end up with insurmountable engineering challenges, including available wafer size, device yield, and crosstalk, all constraining the scalability of monolithic quantum processor designs. This suggests the desirability of developing alternative modular approaches, where smaller-scale quantum modules are individually constructed and calibrated, then assembled into a larger architecture using high-quality quantum coherent interconnects [341][342][343][344][345]. Several recent experiments have demonstrated deterministic quantum state transfers (QSTs) between two superconducting quantum modules, with interconnects provided by commercial niobium-titanium (NbTi) superconducting coaxial cables [346][347][348], copper coaxial cables [349], and aluminum waveguides [350], showing fidelities up to %, primarily limited by lossy components including connectors, circulators, and printed circuit board traces.…”

Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package

“…However, such a solution would impose an impractically high density of interconnects wiring the electronics at the array boundary to every single qubit or, in case of sharing of control lines, impractical requirements on qubit uniformity, increased noise (crosstalk) and limited yield. A viable architectural alternative proposed by leading quantum computing experts is to split the quantum processor into smaller cores (named here as Qcores) to be sparsely placed [4]- [6]. This approach is by no means trivial, though, as it implies the development of (i) appropriate architectural means to seamlessly manage multiple quantum cores, i.e.…”

“…Exact approaches for small-size quantum circuits and approximate mapping solutions using heuristics for larger quantum circuits have been developed for specific single-core NISQ devices [28], [29]. Recently, the first compiler techniques for mapping and scheduling quantum algorithms onto connectivity-simplified multi-core quantum architectures have been proposed [30], [31] as distributed or modular architectural approaches are becoming more prominent for scalingup quantum hardware [4]- [6], [32]. These mapping solutions all focus on multi-Qcore architectures that assume all-to-all intra-and inter-core connectivity with unlimited and ideal communication resources and a fixed and invariant interconnection network.…”

Scaling Superconducting Quantum Computers with Chiplet Architectures

“…Methods to better characterize and reduce quantum defects that impact coherence [60], [67], [84] are also relevant as they aim to make qubits better-suited for future, large-scale computation. Studies are emerging that model linked quantum devices to better understand distributed QC performance in SC-based systems [42] and trapped-ion devices [54]. Finally, work exists that outlines architecture considerations for teleportation-based quantum multi-core systems [70] and explores latency and scaling trade-offs needed in a technology-agnostic manner for effective communication and computation in such systems [71], [72].…”